Inspection Guided Overlay Metrology Sampling
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Solution Overview
Problem
Current metrology sampling plans for semiconductor wafers are limited by fixed locations, which can miss subtle variations and are time-consuming, leading to inadequate process monitoring and control, especially as semiconductor device dimensions decrease.
Innovation Solution
An inspection-guided overlay metrology method and system that dynamically identifies defects and overlay errors across the wafer, generating a sampling plan based on the proximity of defects to identified overlay sites, allowing for more sensitive and efficient measurement coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If fixed location metrology sampling is used, then measurement coverage is simplified, but subtle variations and critical dimension excursions are missed
Solution Approach 1:
The patent implements dynamic sampling plan generation that adapts to each wafer's specific defect characteristics. Instead of using fixed, static sampling locations, the system dynamically identifies defect regions through inspection data and generates customized sampling plans that target areas with defects or potential overlay errors. This dynamic adaptation enables detection of subtle variations while maintaining efficient measurement coverage.
Solution Approach 2:
The patent applies local quality by differentiating sampling strategies based on local defect characteristics. Different regions of the wafer receive different sampling densities and methodologies based on their specific needs identified through inspection. Areas with defects or high variability receive enhanced sampling attention, while stable regions use standard sampling, optimizing both detection precision and overall efficiency.
2Reliability
If comprehensive defect inspection is performed across the entire wafer, then detection sensitivity is improved, but inspection time increases
Solution Approach 1:
The patent performs preliminary defect inspection and identification before generating the metrology sampling plan. By conducting a preliminary scan to locate defects and high-risk areas, the system prepares targeted sampling locations in advance. This preliminary action enables the subsequent metrology measurements to focus only on critical regions, maintaining high detection reliability while significantly reducing the time required for comprehensive inspection.
Solution Approach 2:
The patent segments the wafer inspection process into distinct phases: preliminary defect identification, sampling plan generation, and targeted metrology measurement. This segmentation allows the system to perform rapid preliminary scanning to identify critical areas, then concentrate detailed measurements only on those specific regions, rather than uniformly inspecting the entire wafer, thus reducing total inspection time while maintaining reliability.
3Measurement precision
If multiple recipes are optimized for inspection and review tools, then defect classification accuracy is improved, but setup time and complexity increase
Solution Approach 1:
The patent merges the inspection and metrology workflows by integrating defect identification results directly into sampling plan generation. The system combines data from inspection tools with overlay metrology measurements in a unified process, eliminating the need for separate, independently optimized recipes for each tool. This integration maintains defect classification accuracy while reducing setup time through streamlined, coordinated operation.
Solution Approach 2:
The patent creates a universal sampling plan generation system that works across different defect types and inspection scenarios. The system uses a common framework that adapts to various defect characteristics and tool configurations, eliminating the need to develop and optimize separate specialized recipes for each case. This multi-functional approach maintains accuracy across different situations while significantly reducing setup complexity and time.
Data Source
AI summary
Inspection guided overlay metrology may include performing a pattern search in order to identify a predetermined pattern on a semiconductor wafer, generating a care area for all instances of the predetermined pattern on the semiconductor wafer, identifying defects within generated care areas by performing an inspection scan of each of the generated care areas, wherein the inspection scan includes a low-threshold or a high sensitivity inspection scan, identifying overlay sites of the predetermined pattern of the semiconductor wafer having a measured overlay error larger than a selected overlay specification utilizing a defect inspection technique, comparing location data of the identified defects of a generated care area to location data of the identified overlay sites within the generated care area in order to identify one or more locations wherein the defects are proximate to the identified overlay sites, and generating a metrology sampling plan based on the identified locations.