Semiconductor Inspection Wiring Layout for Dicing Crack Detection
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Solution Overview
Problem
The existing methods for detecting chipping or cracking in power chips during the dicing process are inefficient due to the increased area of ineffective regions caused by inspection wiring, leading to longer inspection times and potential undetection of defects, especially as wafer diameters increase.
Innovation Solution
A semiconductor device design where inspection wiring is placed in the ineffective region surrounding the effective region, electrically connected to the rear surface electrode, allowing for detection of chipping or cracking by measuring current flow without increasing the effective region's area, thus reducing chip size and detection time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If inspection wiring is provided on the outer periphery of the chip region to detect chipping and cracking, then defect detection capability is improved, but the area of the ineffective region increases, causing the chip size to increase
Solution Approach 1:
The patent merges the inspection wiring with the power supply wiring structure. The inspection wiring is integrated into the ineffective region and shares the same layout and routing as the power supply wiring, allowing both inspection and power supply functions to coexist without increasing chip size. This is achieved by providing inspection wiring that extends from the front surface to the back surface of the chip, connected to the rear surface electrode, similar to the power supply wiring configuration.
Solution Approach 2:
The rear surface electrode serves multiple functions: it acts as both a power supply electrode and an inspection electrode. By connecting both the power supply wiring and inspection wiring to the same rear surface electrode, the system achieves multi-functionality where a single structural element supports both operational and inspection purposes, eliminating the need for separate dedicated inspection structures that would increase chip area.
2Reliability
If inspection wiring is provided in the ineffective region, then defect detection is enabled, but the area of the effective region decreases relative to the total chip area
Solution Approach 1:
The patent applies local quality by confining the inspection wiring exclusively to the ineffective region, which is the area surrounding the effective region on the chip periphery. This ensures that the inspection wiring occupies only the space that would otherwise be non-functional, thereby maintaining the effective region's area and its proportion to the total chip area while still enabling defect detection capability.
3Productivity
If wafer diameter is increased to improve manufacturing efficiency, then production capacity is improved, but inspection time increases, making total inspection difficult within limited time
Solution Approach 1:
The patent replaces the conventional optical microscope-based visual inspection system with an electrical resistance measurement system. Instead of using optical equipment to visually examine each chip for chipping and cracking, the system uses electrical resistance measurements through the inspection wiring to detect defects. This substitution dramatically reduces inspection time and enables efficient inspection of large-diameter wafers with many chips, thereby supporting high production capacity while minimizing inspection time loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design narrows the area of inspection wiring, reducing chip size and energy loss while effectively detecting defects that conventional methods may miss, particularly in wide bandgap semiconductors like SiC.
Implementation Method 1
cracks generated during dicing are detectable by measuring the resistance value of the inspection wiring
Data Source
AI summary
An object is to provide a semiconductor device in which the area of inspection wiring for detecting chipping, cracks, or the like is narrowed. The semiconductor device includes a semiconductor substrate including an effective region including a semiconductor element and an ineffective region provided on a circumference of the effective region on a front surface thereof, and a rear surface electrode on a rear surface thereof; and inspection wiring provided in the ineffective region on the front surface of the semiconductor substrate so as to surround an outer periphery of the effective region. The inspection wiring is electrically connected to the rear surface electrode in such a manner that one end of the inspection wiring is in contact with the semiconductor layer which is provided in the ineffective region on the front surface of the semiconductor substrate and electrically connected to the rear surface electrode.