Installation Cache for Die-Stacked DRAM Latency Reduction
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Solution Overview
Problem
Die-stacked DRAM memory with row-based access experiences high access latency due to activation, read, and pre-charge command sequences, making prefetching techniques less effective and increasing cache miss rates.
Innovation Solution
Implementing an installation cache with lower latency than the L3 cache, allowing data to be loaded simultaneously or serially into both the installation cache and the L3 cache, and returning data from the installation cache when it has not completely loaded into the L3 cache, thereby reducing cache misses and system performance issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If die-stacked DRAM memory is used as last-level cache with row-based access, then cache capacity is increased, but access latency increases due to activation, read and pre-charge command sequences
Solution Approach 1:
The patent segments the cache system into two distinct components: an installation cache for holding data during loading, and a L3 cache for actual data storage. This segmentation allows the installation cache to operate independently with faster access, while the L3 cache provides the large capacity needed, resolving the contradiction between capacity and latency.
Solution Approach 2:
The installation cache acts as an intermediary between main memory and the L3 cache. Data is first loaded into the installation cache from main memory, then transferred to the L3 cache. This intermediary allows the system to benefit from both fast access (installation cache) and high capacity (L3 cache), eliminating the need to choose between the two.
2Reliability
If prefetching techniques are used to reduce cache miss rates, then data availability is improved, but effectiveness decreases due to high access latency in die-stacked DRAM
Solution Approach 1:
The installation cache enables preliminary action by loading data into this intermediate cache before the L3 cache is ready to receive it. This allows the system to prepare data in advance without waiting for the L3 cache to be fully ready, improving prefetching effectiveness while managing the high latency of die-stacked DRAM.
3Device complexity
If data is loaded sequentially into L3 cache only, then cache structure is simplified, but system performance degrades due to high latency and busy L3 cache
Solution Approach 1:
The patent divides the data loading path into two segments: installation cache for initial loading and L3 cache for final storage. This segmentation improves system performance by allowing parallel operations and reducing blocking, while adding only minimal structural complexity compared to a single-cache approach.
Data Source
AI summary
Data caching methods and systems are provided. The data cache method loads data into an installation cache and a cache (simultaneously or serially) and returns data from the installation cache when the data has not completely loaded into the cache. The data cache system includes a processor, a memory coupled to the processor, a cache coupled to the processor and the memory and an installation cache coupled to the processor and the memory. The system is configured to load data from the memory into the installation cache and the cache (simultaneously or serially) and return data from the installation cache to the processor when the data has not completely loaded into the cache.