Instruction Bus Monitoring for Runtime Fault Injection Detection
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Solution Overview
Problem
Existing security mechanisms in IoT devices fail to validate processor instructions during runtime, leaving them vulnerable to malicious attacks such as fault injection, which can bypass authentication mechanisms and expose resources to unauthorized access.
Innovation Solution
Implementing a hardware-based execution monitor on the chip that validates processor instructions by comparing fetched addresses and instructions with a pre-compiled list, using cyclic redundancy checks (CRC) and timeouts to ensure the correct execution sequence, and triggering interrupts or resets in case of mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a hardware-based execution monitor is implemented to validate processor instructions, then security against fault injection attacks is improved, but device complexity increases
Solution Approach 1:
The patent pre-compiles expected instruction sequences and stores them in a validation buffer before execution. The execution monitor compares incoming instructions against these pre-established sequences, allowing validation without complex real-time analysis. This preliminary preparation reduces the complexity of the validation logic during runtime.
Solution Approach 2:
The execution monitor acts as an intermediary component between the processor core and the instruction memory. It intercepts instruction fetches, validates them against the pre-compiled sequences, and either allows or blocks execution. This intermediary approach isolates the security validation logic from the main processor, reducing overall device complexity while maintaining strong security.
2Reliability
If instruction validation is performed for every fetched instruction, then protection against malicious attacks is improved, but processing speed decreases
Solution Approach 1:
The patent validates instructions against pre-compiled sequences only when there is a mismatch detected or at critical checkpoints, rather than performing full validation on every single instruction. This partial validation approach maintains security while reducing the overhead that would slow down processing, allowing normal execution to proceed at full speed for validated instruction sequences.
Data Source
AI summary
Systems and methods for validating operation of a software sequence may include: monitoring signals on a bus of a processor, comparing the contents of the signals on the bus to pre-stored information from compile time. If the comparing generates a match, that may indicate that the software sequence is operating as intended. However, if the comparing generates a mismatch, that may indicate that the software sequence is not operating as intended and may, in fact, indicate a malicious use. Further actions can be taken in response to a mismatch, including resetting a processor, issuing an interrupt, and the like.