Instruction Cache Allocation Control for Side-Channel Attack Mitigation
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Solution Overview
Problem
Speculative execution in data processing apparatuses can lead to vulnerability in instruction cache storage, allowing cache timing side-channel attacks where untrusted code can exploit speculative memory reads to leak sensitive information by determining cache allocation patterns.
Innovation Solution
Implementing cache control circuitry that selectively allocates instructions into the instruction cache only if they are of a specific type, such as a 'landing pad' instruction, thereby preventing unauthorized allocation and mitigating the risk of cache timing side-channel attacks by ensuring only legitimate instructions are cached.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If speculative execution is enabled to improve processing speed, then productivity is improved, but security against cache timing side-channel attacks deteriorates
Solution Approach 1:
The patent applies preliminary anti-action by implementing a cache allocation policy that proactively prevents allocation of instructions fetched from branch target addresses to the instruction cache. This preemptive measure blocks the attack vector before it can be exploited, while still allowing speculative execution to proceed for performance optimization. The system anticipates potential side-channel attacks and neutralizes them in advance through selective cache allocation restrictions.
2Productivity
If instructions are allocated into instruction cache storage to improve execution speed, then productivity is improved, but security against information leakage deteriorates
Solution Approach 1:
The patent applies local quality by implementing differential cache allocation policies for different instruction types and memory regions. Specifically, instructions fetched from branch target addresses are excluded from cache allocation, while other instructions continue to be cached normally. This localized restriction applies security controls only where needed (at branch targets) without compromising overall cache performance or execution speed for legitimate code paths.
3Reliability
If cache control restrictions are applied to prevent unauthorized allocation, then security is improved, but device complexity increases
Solution Approach 1:
The patent applies self-service by implementing cache allocation control that leverages existing processor components and mechanisms. The cache control logic utilizes information already available in the processor (such as branch target address identification) to make allocation decisions, rather than requiring entirely new control infrastructure. This approach achieves enhanced security through intelligent use of existing resources, minimizing the increase in device complexity.
Data Source
AI summary
An apparatus and method are provided for controlling allocation of instructions into an instruction cache storage. The apparatus comprises processing circuitry to execute instructions, fetch circuitry to fetch instructions from memory for execution by the processing circuitry, and an instruction cache storage to store instructions fetched from the memory by the fetch circuitry. Cache control circuitry is responsive to the fetch circuitry fetching a target instruction from a memory address determined as a target address of an instruction flow changing instruction, at least when the memory address is within a specific address range, to prevent allocation of the fetched target instruction into the instruction cache storage unless the fetched target instruction is at least one specific type of instruction. It has been found that such an approach can inhibit the performance of speculation-based caching timing side-channel attacks.