Instruction Cache Branch Handling in Semiconductor Devices
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Solution Overview
Problem
In microprocessor systems, the increase in clock frequency leads to higher power consumption and chip area, with memory access delays becoming a bottleneck, especially in systems with large capacity memory, where resetting the instruction queue for branch instructions results in unnecessary memory access and power consumption during short loop processing.
Innovation Solution
The semiconductor device reuses instruction codes stored in the instruction queue during short loop processing by fetching the branch destination instruction from the instruction cache instead of the memory, optimizing power consumption by reducing unnecessary memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the instruction queue is reset to fetch instructions from memory for branch instructions, then the CPU can execute branch instructions correctly, but unnecessary memory access occurs during short loop processing causing increased power consumption
Solution Approach 1:
The system performs preliminary actions by pre-fetching instructions into the instruction queue before they are needed. When a branch instruction is encountered, the instruction queue already contains the necessary instructions, eliminating the need to reset and re-fetch from memory, thus reducing power consumption while maintaining correct execution
Solution Approach 2:
The instruction queue acts as an intermediary buffer between memory and the CPU execution units. By maintaining instructions in this intermediary structure, the system avoids direct memory access for frequently executed branch instructions, reducing power consumption while ensuring correct branch handling
2Productivity
If the instruction queue is reset for branch instructions, then the CPU can fetch new instructions, but memory access delay increases during short loop processing
Solution Approach 1:
Instructions are pre-fetched and stored in the instruction queue before the CPU needs to execute them. This preliminary action eliminates the need for time-consuming memory access during short loop processing, maintaining high productivity while reducing delay
Solution Approach 2:
The system creates a copy of instructions in the instruction queue rather than continuously accessing the original memory. This copying approach allows the CPU to execute instructions from the queue without repeated memory access, reducing time loss while maintaining fetch efficiency
3Ease of operation
If the instruction queue is reset to fetch branch destination instructions, then the CPU can execute the branch, but chip area and power consumption increase due to repeated memory access
Solution Approach 1:
The instruction queue is pre-filled with instructions before branch execution is needed. This preliminary action allows the CPU to handle branch instructions easily by simply reading from the queue rather than performing complex memory access operations, reducing both ease of operation difficulty and power consumption
Data Source
AI summary
A semiconductor device includes a memory for storing a plurality of instructions therein, an instruction queue which temporarily stores the instructions fetched from the memory therein, a central processing unit which executes the instruction supplied from the instruction queue, an instruction cache which stores therein the instructions executed in the past by the central processing unit, and a control circuit which controls fetching of each instruction. When the central processing unit executes a branch instruction, and an instruction of a branch destination is being in the instruction cache and an instruction following the instruction of the branch destination is stored in the instruction queue, the control circuit causes the instruction queue to fetch the instruction of the branch destination from the instruction cache and causes the instruction queue not to fetch the instruction following the instruction of the branch destination.