Instruction Cache Directory Access Suppression
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Solution Overview
Problem
Current computing environments face inefficiencies in processing instruction fetches due to unnecessary directory accesses in instruction caches, leading to increased power dissipation and heat generation, especially when accessing sequential cache lines.
Innovation Solution
A method is introduced to selectively suppress instruction cache-related directory accesses by determining if the next instruction fetch is within the same cache line as the previous fetch, generating a known-to-hit signal to avoid redundant directory checks, and maintaining validity information for each cache line segment to ensure accurate cache hits without performing unnecessary lookups.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If directory accesses are performed for every instruction fetch to verify cache line validity, then cache access reliability is improved, but power dissipation increases
Solution Approach 1:
The patent performs directory access preliminarily for a first instruction fetch to obtain validity information about the cache line, then reuses this information for subsequent instruction fetches from the same cache line, avoiding redundant directory accesses and reducing power dissipation while maintaining reliability
Solution Approach 2:
The validity information obtained from directory access serves multiple purposes: it verifies cache line correctness for the first instruction and is reused to suppress directory accesses for subsequent instructions from the same cache line, making the directory access operation multi-functional
2Measurement precision
If directory accesses are performed for every instruction fetch to verify cache line validity, then cache access accuracy is improved, but processing speed deteriorates
Solution Approach 1:
The patent performs directory access preliminarily for the first instruction fetch to establish validity information, then uses this pre-obtained information to quickly process subsequent instruction fetches from the same cache line without repeating the directory access, thereby improving processing speed while maintaining accuracy
Solution Approach 2:
The system uses the validity information obtained from the first directory access to serve subsequent cache access decisions within the same cache line, making the system self-sufficient and eliminating the need for repeated external directory accesses
3Use of energy by moving object
If directory accesses are suppressed for sequential cache line accesses, then power dissipation is reduced, but cache access reliability may deteriorate
Solution Approach 1:
The patent applies directory access suppression selectively only to subsequent instructions within the same cache line after the first instruction has triggered a directory access, while maintaining full directory access for instructions from different cache lines, thus locally optimizing power consumption without compromising overall reliability
Solution Approach 2:
The system uses feedback from the first directory access result (validity information) to control whether subsequent directory accesses are suppressed, creating a feedback mechanism that maintains reliability by only suppressing accesses when validity is confirmed
Data Source
AI summary
Processing of an instruction fetch from an instruction cache is provided, which includes: determining whether the next instruction fetch is in a same cache line of the instruction cache as a last instruction fetch; and based, at least in part, on determining that the next instruction fetch is in the same cache line, suppressing for the next instruction fetch one or more instruction cache-related directory accesses, and forcing for the next instruction an address match signal for the same cache line. The suppressing may include generating a known-to-hit signal where the next fetch is in the same cache line, and the last fetch is not a branch instruction, and issuing an instruction cache hit where a cache line segment of the same cache line having the next instruction has a valid validity bit, the valid validity bit having been retrieved and maintained based on a most-recent, instruction cache-directory-accessed fetch.