Instruction Cache Logic Testing With Counter-Based Defect Detection
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Solution Overview
Problem
Conventional software testing of cache logic circuits requires emptying the memory content before each test, leading to inefficiencies and the need for costly hardware solutions to detect hardware defects, which disrupts continuous use of the cache memory.
Innovation Solution
A method involving the use of cache access counters to increment values during instruction or data execution, blocking unintended executions or readings, and comparing final counter values with expected results to detect defects without emptying the cache memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional software testing of cache logic circuits is performed by emptying memory content before each test, then defect detection capability is improved, but productivity deteriorates due to loss of stored data and need for re-storing
Solution Approach 1:
The patent applies preliminary action by recording the initial value of the cache access counter before executing the test sequence. This preliminary recording allows the system to later compare the counter's final value with the expected value (initial value + number of test instructions), enabling defect detection without needing to empty the cache memory. The preliminary capture of the counter state provides a reference point for validation.
Solution Approach 2:
The patent uses copying by creating a software-based test mechanism that copies the functionality of hardware testing solutions. Instead of using expensive hardware BIST systems or emptying the cache, the invention copies the essential testing capability through software that monitors cache access counts and validates them against expected values, achieving similar defect detection without the drawbacks of conventional approaches.
2Reliability
If hardware solutions like BIST systems or cache redundancy are used to detect defects, then reliability is improved, but device complexity and cost increase
Solution Approach 1:
The patent applies mechanics substitution by replacing complex hardware testing mechanisms (such as BIST systems or redundancy circuits) with a software-based solution. The invention uses software to execute a test sequence, monitor cache access counts through a counter, and validate the results by comparing the counter's final value with the expected value. This substitution eliminates the need for additional hardware components while maintaining defect detection capability.
Solution Approach 2:
The patent implements self-service by enabling the cache logic circuit to participate in its own testing through the software mechanism. The counter, which is part of the cache system, automatically increments during the test sequence execution, and the software compares this automatically generated data against expected values. The system uses its own internal resources (the counter and the cache access mechanism) to perform the testing function.
3Measurement precision
If cache memory is emptied before testing, then measurement precision is improved for defect detection, but loss of time occurs due to re-storing data
Solution Approach 1:
The patent applies preliminary action by capturing the initial value of the cache access counter before the test sequence is executed. This preliminary capture establishes a baseline that enables accurate defect detection without requiring the cache to be emptied. The initial counter value serves as a reference point for calculating the expected final value, ensuring measurement precision while avoiding time loss from data re-storing.
Data Source
AI summary
A computer-implemented method for testing an instruction cache logic circuit of an integrated circuit, comprising: storing in the cache logic circuit a sequence of instructions including M instructions; reading an initial counter value of a cache access counter; executing the sequence of instructions and, for each instruction executed from the cache logic circuit, incrementing the current counter value of the counter; reading a final counter value of the counter; blocking an execution of instructions unintended by the test for a period lasting from reading the initial counter value until reading the final counter value; subtracting the initial counter value from the final counter value, and comparing the result of said subtraction with the value M.