Instruction Cache Power Reduction via MRU Way Selection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing instruction cache implementations face a trade-off between processing speed and power consumption, with parallel approaches increasing power usage for faster performance and serial approaches reducing power but sacrificing speed.
Innovation Solution
The method involves determining the most-recently-used (MRU) way in the instruction cache to efficiently access data, activating only the MRU way instead of all ways in a cacheline set, which reduces power consumption while maintaining performance by looking up the MRU way in parallel with tag array access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If all data locations in the data array that correspond to the set of cachelines are activated in parallel to fetch data, then processing speed is improved, but power consumption is increased
Solution Approach 1:
The patent extracts and activates only the specific data location corresponding to the matched cacheline set from the data array, rather than activating all data locations in parallel. This selective activation reduces power consumption while maintaining the speed benefit of parallel tag array access, as only the necessary data location is powered up after the tag match is identified.
Solution Approach 2:
The patent dynamically adjusts the activation of data array locations based on the results of tag array matching. Instead of static parallel activation of all locations, the system dynamically activates only the specific location needed after identifying a cache hit, optimizing the balance between speed and power consumption based on actual access patterns.
2Use of energy by moving object
If only one location in the data array is activated to reduce power consumption, then power consumption is reduced, but processing speed is sacrificed due to serial access requirements
Solution Approach 1:
The patent segments the data array access into two phases: first, parallel tag array access to identify the matched cacheline set; second, selective data array access only at the specific location corresponding to the match. This segmentation allows the system to maintain parallel processing benefits while minimizing power consumption by activating only the necessary data location after identification.
3Use of energy by moving object
If serial approach is used to activate only one data array location, then power consumption is reduced, but multiple clock cycles are required to identify and access the matching data location
Solution Approach 1:
The patent performs preliminary parallel tag array access to identify the matched cacheline set before activating the specific data array location. This preliminary identification step enables subsequent selective data access to proceed efficiently, reducing both power consumption and access time compared to purely serial approaches.
Data Source
AI summary
In one embodiment, a method for controlling an instruction cache including a least-recently-used bits array, a tag array, and a data array, includes looking up, in the least-recently-used bits array, least-recently-used bits for each of a plurality of cacheline sets in the instruction cache, determining a most-recently-used way in a designated cacheline set of the plurality of cacheline sets based on the least-recently-used bits for the designated cacheline, looking up, in the tag array, tags for one or more ways in the designated cacheline set, looking up, in the data array, data stored in the most-recently-used way in the designated cacheline set, and if there is a cache hit in the most-recently-used way, retrieving the data stored in the most-recently-used way from the data array.