Instruction Cache Non-Cacheable Data Storage
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Solution Overview
Problem
Current data processing systems face inefficiencies in storing non-cacheable instruction data, leading to increased silicon area requirements and potential processor stalls due to the need for additional buffering and re-fetching of infrequent non-cacheable instructions.
Innovation Solution
The proposed solution involves utilizing the existing instruction cache to temporarily store non-cacheable instruction data, marking cache lines as invalid to prevent cache hits, and maintaining records for retrieval, allowing non-cacheable instructions to be re-fetched from memory when needed, thus avoiding the need for additional buffer storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If separate buffer storage is provided for non-cacheable instructions, then temporary storage capability is improved, but silicon area increases
Solution Approach 1:
The instruction cache is designed to handle both cacheable and non-cacheable instructions using the same storage structure. The cache control circuitry determines the instruction type and manages storage accordingly, allowing the same physical storage resources to serve multiple purposes without requiring separate buffer structures.
Solution Approach 2:
The patent merges the storage functionality for non-cacheable instructions with the existing instruction cache structure. Instead of providing separate buffer storage, the solution combines both instruction types into a single cache system, utilizing the same data storage resources for both cacheable and non-cacheable instruction temporary storage.
2Area of stationary object
If instruction cache is used for non-cacheable instructions, then silicon area is reduced, but cache operation complexity increases
Solution Approach 1:
The cache control circuitry acts as an intermediary that manages the interaction between cacheable and non-cacheable instructions. It determines the instruction type, selects appropriate cache lines, and manages valid/invalid flags to prevent cache hits for non-cacheable instructions, thereby handling the increased operational complexity within the control logic.
Solution Approach 2:
Different cache lines are assigned different qualities based on their content type. Cache lines storing non-cacheable instructions are marked as invalid to prevent cache hits, while cache lines storing cacheable instructions maintain normal valid/invalid functionality. This local differentiation allows the system to handle mixed instruction types without requiring complete redesign of the cache operation.
3Quantity of substance
If non-cacheable instructions are stored in cache, then storage efficiency is improved, but cache hit accuracy deteriorates
Solution Approach 1:
The system uses valid/invalid flags as visual indicators (analogous to color changes) to distinguish between cacheable and non-cacheable instruction storage. When a cache line contains non-cacheable instructions, the invalid flag is set, effectively marking it as unavailable for cache hits. This allows the cache structure to physically store both types of instructions while maintaining logical separation through status indicators.
Data Source
AI summary
An instruction cache stores cacheable instructions for access by a processing circuitry, the instruction cache having a data storage comprising a plurality of cache lines and a tag storage comprising a plurality of tag entries, each cache line for storing instruction data specifying a plurality of cacheable instructions, and each tag entry for storing an address identifier for the instruction data stored in an associated cache line. The instruction cache including valid flag storage for identifying whether each cache line is valid. Instruction cache control circuitry is arranged to store within a selected cache line of the data storage the instruction data for a plurality of cacheable instructions as retrieved from memory, to store within the tag entry associated with that selected cache line the address identifier for that stored instruction data, and to identify that selected cache line as valid within the valid flag storage.