Instruction Cache Line Sharing Across Threads
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Solution Overview
Problem
In multi-threaded processing environments, there is no effective way to determine which instruction cache lines are shareable across process boundaries, resulting in instruction cache footprints that cannot be shared between different processor threads.
Innovation Solution
The use of instruction cache set/way pointers and a tracking table allows for the sharing of instruction cache lines between multiple threads by deriving set/way pointers from system memory addresses and updating the instruction cache directory to indicate shared cache lines, even without access to real addresses or translation information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If instruction cache lines are marked private per thread, then thread-specific instruction access is ensured, but cache footprint cannot be shared between different processor threads
Solution Approach 1:
The patent introduces a tracking table as an intermediary data structure that stores set/way pointers to monitor which cache lines are shared across threads. This mediator enables the system to track and manage shared cache lines without requiring complex hardware modifications to the cache itself, thus resolving the contradiction between enabling cache sharing and maintaining manageable complexity
Solution Approach 2:
The patent adds a new dimension of tracking by storing set/way pointers in a tracking table alongside thread identifiers. This additional dimensional layer allows the system to monitor cache line sharing across multiple threads without modifying the fundamental cache structure, enabling cache footprint sharing while keeping the cache management system relatively simple
2Measurement precision
If set/way pointers are stored in instruction cache directory, then cache line location is tracked, but real address translation information is not accessible
Solution Approach 1:
The patent creates a copy of the essential cache line identification information (set/way pointers) and stores it in the tracking table. This copy is sufficient for tracking purposes and enabling cache sharing decisions, while the system accepts that the complete real address translation information is not preserved in this structure. The copy provides the necessary precision for cache line identification without requiring full address translation data
Data Source
AI summary
Aspects are provided for sharing instruction cache footprint between multiple threads using instruction cache set/way pointers and a tracking table. The tracking table is built up over time for shared pages, even when the instruction cache has no access to real addresses or translation information. A set/way pointer to an instruction cache line is derived from the system memory address associated with a first thread's instruction fetch. The set/way pointer is stored as a surrogate for the system memory address in both an instruction cache directory (IDIR) and a tracking table. Another set/way pointer to an instruction cache line is derived from the system memory address associated with a second thread's instruction fetch. A match is detected between the set/way pointer and the other set/way pointer. The instruction cache directory is updated to indicate that the instruction cache line is shared between multiple threads.