Instruction Cache Track Table for Multi-Way Set Associative Systems
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Solution Overview
Problem
Current cache systems face performance bottlenecks due to cache misses, particularly in multi-way set associative caches, where power and speed limitations lead to inefficiencies in accessing and comparing contents and tags across cache sets, resulting in a significant gap between processor speed and memory speed.
Innovation Solution
A high-performance instruction cache method is introduced, utilizing a track table to manage instruction blocks between a faster first memory and a slower second memory, where instruction information is extracted to create tracks, allowing for efficient filling of instructions into the first memory without the need for tag-matching operations, and a correlation table aids in memory replacement by recording source addresses for efficient storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a multi-way set associative cache is used to improve cache hit rate, then the cache capacity and associativity are increased, but the power consumption and access time increase due to reading and comparing contents and tags from all cache sets simultaneously
Solution Approach 1:
The patent divides the cache access process into two independent stages: (1) reading only tag information from cache sets based on index address, and (2) reading content information only after tag comparison succeeds. This segmentation eliminates the need to read and compare all tag-content pairs simultaneously, reducing power consumption while maintaining cache hit rate.
Solution Approach 2:
The patent performs tag comparison before reading content information. By preliminarily checking whether the tag matches the requested address, the system avoids the unnecessary power consumption of reading and comparing full content information from all cache sets, while still achieving the same cache hit rate.
2Reliability
If a multi-way set associative cache is used to improve cache hit rate, then the cache capacity and associativity are increased, but the access speed decreases due to the need to read and compare all cache sets in parallel
Solution Approach 1:
The patent segments the cache access into two phases: tag reading/comparison phase and content reading phase. This allows the system to quickly determine cache hits/misses based on tag comparison alone, improving access speed for hit cases while maintaining the same cache hit rate through proper cache structure.
Solution Approach 2:
By performing tag comparison as a preliminary step before content access, the patent enables faster determination of cache validity. This preliminary action reduces the critical path delay for cache hits while maintaining the same hit rate, as tags are smaller and can be compared faster than full content data.
3Quantity of substance
If traditional cache addressing is used with tag comparison, then cache capacity can be increased, but the processor speed-memory speed gap widens due to cache misses and comparison overhead
Solution Approach 1:
The patent applies segmentation to reduce the overhead of cache operations by separating tag and content access. This allows larger cache capacities to be implemented with reduced access latency, as the critical path is dominated by fast tag comparison rather than slow content reading from all sets, thereby narrowing the processor-memory speed gap.
Solution Approach 2:
By performing tag comparison preliminarily before content access, the patent reduces the average memory access time. This preliminary validation allows the system to handle larger cache capacities efficiently, as miss detection occurs faster, enabling more aggressive caching strategies that narrow the processor-memory speed gap.
Data Source
AI summary
A high-performance instruction cache method based on extracting instruction information and store in a track table. The method enables reading of all levels of cache, including the last level cache, without performing tag matching. The method enables the content of the track table addressing directly instruction memories in both track cache or in set associative organization. Further, the method includes a memory replacement method using a track table, a first memory containing multiple rows instruction blocks, and a correlation table. The correlation table records source addresses of rows indexing a target row and the lower level memory address of the target row. During replacement of a first memory row, the lower level memory address of the target row replaces the address of the target row in the source row of the track table, and therefore preserve the indexing relationship recorded in the track table despite the replacement.