Instruction Control for Early Cache Reads Under Address Dependency

The patent applies preliminary action by allowing the read operation of a memory access instruction to be executed in advance before the write operation of the preceding instruction completes. The instruction transmission controller transmits the current memory access instruction to the data cache unit early, and the data cache unit performs the read operation ahead of time, storing data in a blocked state. This eliminates the waiting time for dependency release while ensuring data accuracy is maintained through the blocking mechanism that prevents premature data use.

The patent introduces a blocking signal as an intermediary mechanism between the early read operation and data usage. The instruction transmission controller sends a blocking signal to the data cache unit when transmitting the current memory access instruction. This blocking signal acts as a mediator that allows the read operation to complete and data to be stored in the data cache unit, but prevents the data from being used or forwarded until the write operation completes and the blocking signal is cleared. This resolves the contradiction by enabling early execution while guaranteeing data accuracy.

The patent applies preliminary action by separating the read operation from the write operation in time. The instruction transmission controller transmits the current memory access instruction to the data cache unit in advance, allowing the read operation to execute before the preceding instruction's write operation completes. The data cache unit stores the read data in a blocked state, maintaining data dependency accuracy. Meanwhile, the early execution of the read operation hides the memory access delay, significantly improving data supply speed to meet processor requirements.