Instruction Controller Pipelines for Parallel Processing
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Solution Overview
Problem
Existing data processing systems face delays in executing sequences of instructions, particularly when these sequences include looped instructions, due to serial execution of instructions and reliance on external memory operations, which is problematic in low-latency applications like wireless telecommunications.
Innovation Solution
A method and apparatus for delivering instructions to parallel function units using an instruction controller with multiple pipelines and registers, where instructions are timed and scheduled to minimize delay between sequences, ensuring that instructions from different sequences do not overlap in execution, allowing for efficient parallel execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If instructions are executed serially in order of receipt, then the execution order is simple and deterministic, but the processing speed and throughput are limited
Solution Approach 1:
The instruction delivery mechanism is segmented into multiple independent instruction pipelines (first instruction pipeline, second instruction pipeline, etc.), each capable of independently delivering instructions to function units. This segmentation allows parallel instruction delivery without requiring complex centralized control, thus improving processing speed while keeping individual pipeline complexity manageable.
Solution Approach 2:
The patent transitions from single-dimension serial instruction execution to multi-dimension parallel execution by introducing multiple instruction pipelines that can operate simultaneously. Instructions from different sequences can be delivered through different pipelines in parallel, effectively adding a temporal dimension to instruction execution and overcoming the serial execution bottleneck.
2Productivity
If multiple instruction sequences are interleaved to reduce delays, then parallel execution efficiency improves, but ensuring correct execution order becomes more difficult
Solution Approach 1:
Instructions are tagged with sequence identification information and timing values before being delivered to pipelines. This preliminary tagging allows the system to pre-establish the execution order requirements, ensuring that even when instructions from different sequences are interleaved in parallel, their correct execution order is maintained through the embedded timing and sequence metadata.
Solution Approach 2:
The system uses feedback mechanisms where instruction delivery is controlled based on timing values and sequence identification. The instruction controller monitors the state of multiple pipelines and adjusts instruction delivery timing accordingly, ensuring that instructions execute in the correct order while maintaining parallel execution efficiency.
3Quantity of substance
If external memory operations are used for data input/output, then data storage capacity is sufficient, but processing latency increases
Solution Approach 1:
The patent implements a nested memory structure where registers are embedded within the processing element, and these registers can be nested within larger memory systems. This nesting allows frequently accessed data to be stored in fast, on-chip registers, reducing the need for slow external memory operations while maintaining sufficient storage capacity through the hierarchical structure.
Solution Approach 2:
Registers act as intermediaries between external memory and function units. Instead of directly accessing external memory for every operation, data is first loaded into registers which serve as a buffer and cache layer. This intermediary structure reduces processing latency by providing fast access to frequently used data while maintaining the capacity of external memory for larger data sets.
Data Source
AI summary
A processing element comprises a plurality of function units (16) operable to execute respective functions in dependence upon received instructions in parallel with one another. An instruction controller includes an instruction register (41) having a plurality of register entries, each of which is operable to store an instruction word therein, and a plurality of instruction pipelines (42). Each of the pipelines (42) is associated with a function unit (16), and is operable to deliver instructions to the function unit concerned for execution thereby. Each pipeline also includes a timing controller operable to receive timing information for a received instruction, and to determine an initial location in the pipeline into which the instruction is to be loaded, and an instruction handler operable to receive an instruction for the function unit associated with the instruction pipeline concerned, and to load that instruction into the initial location determined by the timing controller.