Assembly Instruction Conversion Reordering for Cross-Architecture Compatibility
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Solution Overview
Problem
JIT compiler-generated machine language for one processor architecture cannot be directly executed on another processor architecture, leading to increased clock cycles when converted, due to dependency relationships between assembly instructions.
Innovation Solution
A method to store and generate machine languages for a second assembly instruction set such that dependent instructions are not adjacent, using a FIFO buffer to reorder generation instructions and translate them into equivalent instructions for the target architecture, preventing pipeline stalls.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If machine language is converted from one instruction set to another instruction set, then the execution program can operate on different processor architectures, but the number of clock cycles increases due to dependency relationships between assembly instructions
Solution Approach 1:
The patent applies preliminary action by analyzing and reordering assembly instructions before generating the target machine language. The instruction reordering unit rearranges instructions to separate dependent instructions, preventing pipeline stalls before execution occurs. This proactive reorganization ensures that when the converted program runs on the target architecture, the instruction pipeline remains full and continuous, avoiding delays that would otherwise occur during execution.
2Adaptability or versatility
If assembly instructions are converted between different instruction sets, then portability across processors is achieved, but pipeline stalls occur due to adjacent dependent instructions
Solution Approach 1:
The patent applies segmentation by dividing the instruction conversion process into distinct functional units: an analysis unit that identifies dependency relationships, a reordering unit that segments and rearranges instructions to break adjacency of dependent instructions, and a generation unit that produces the target machine language. This segmented approach allows systematic optimization of instruction ordering to maintain pipeline efficiency during cross-architecture conversion.
Solution Approach 2:
The patent applies parameter changes by modifying the execution order parameter of assembly instructions during conversion. By changing the sequence in which instructions are arranged in the target program, the system transforms the original instruction stream into an optimized version where dependent instructions are separated, thereby changing the temporal parameters of execution to eliminate pipeline stalls while preserving functional correctness.
Data Source
AI summary
A non-transitory computer-readable medium having stored therein a program for causing a computer to execute a process. The process includes storing a plurality of generation instructions in a storage area for each of a plurality of first assembly instructions, each generation instruction instructing the generation of a machine language of a second assembly instruction that executes processing equivalent to each first assembly instruction, and generating machine languages of a plurality of second assembly instructions so that the machine languages of the second assembly instructions having a dependency relationship do not appear adjacent to each other, according to the plurality of generation instructions in the storage area.