Instruction Decoder Multi-Flow Throughput
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The processing throughput of instruction decoders in processors drops when handling multi-flow instructions, as the separate multi-flow instruction dividing unit interrupts the normal operation of the instruction decoder, leading to reduced efficiency in decoding and issuing instructions.
Innovation Solution
The implementation of a two-stage instruction decoder configuration with a pre-decoder and a main decoder, along with a pre-decoder buffer, allows for the detection and division of multi-flow instructions, optimizing the transfer of instructions to maximize throughput by temporarily storing and reordering instructions in the pre-decoder buffer before processing by the main decoder.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a separate multi-flow instruction dividing unit is used to divide multi-flow instructions, then the instruction can be properly divided into multiple divided instructions, but the processing throughput of the instruction decoder drops because the dividing unit interrupts the normal operation of the instruction decoder
Solution Approach 1:
The patent merges the multi-flow instruction dividing unit with the instruction decoder by integrating the division function into the decoder's slot structure. Each slot in the instruction decoder can independently detect and divide multi-flow instructions, eliminating the need for a separate dividing unit that would interrupt decoder operation. This integration allows the decoder to maintain continuous throughput while still providing multi-flow instruction division capability.
Solution Approach 2:
The patent segments the instruction decoder into multiple slots, where each slot can independently handle instruction decoding and multi-flow division. This segmentation allows parallel processing of multiple instructions simultaneously, so that when one slot is dividing a multi-flow instruction, other slots can continue decoding regular instructions without interruption, thereby maintaining overall throughput.
2Ease of operation
If multi-flow instructions are divided and queued in order by an independent dividing unit, then the divided instructions are properly generated, but the processing to divide and queue the instructions temporarily drops the processing throughput of the instruction decoder
Solution Approach 1:
The patent combines the instruction division and queuing functions within the instruction decoder's slot structure itself. Each slot can detect multi-flow instructions, divide them into multiple divided instructions, and queue them directly in the reservation station without requiring an independent dividing unit. This integration eliminates the throughput drop that would occur with a separate dividing unit.
3Productivity
If the instruction decoder includes multiple slots for parallel decoding, then the decoding processing throughput increases, but the separate multi-flow instruction dividing unit causes interruptions in the pipeline operation
Solution Approach 1:
The patent merges the multi-flow instruction division capability into the instruction decoder's slot structure, so that each slot can independently divide multi-flow instructions without requiring external intervention. This eliminates interruptions to the pipeline operation while maintaining the high throughput enabled by multiple slots for parallel decoding.
Solution Approach 2:
The patent implements preliminary detection and division of multi-flow instructions within each slot before the instruction decoding process begins. By detecting and dividing multi-flow instructions in advance within the slot itself, the system prevents interruptions to the pipeline operation and maintains continuous throughput despite the presence of multiple slots for parallel processing.
Data Source
AI summary
An arithmetic processing unit includes an instruction decoder which decodes a fetch instruction to issue an execution instruction; a reservation station which temporarily stores the execution instruction; and an arithmetic unit which executes the execution instruction, and the fetch instruction includes a multi-flow instruction which is divided into divided instructions and a single instruction. The instruction decoder includes: a pre-decoder including N number of slots each of which divides the multi-flow instruction into divided instructions; a main decoder including N number of slots each of which decodes the instructions to issue an execution instruction; and a pre-decoder buffer including N−K number of slots each of which temporarily stores instructions in the pre-decoder. The instruction decoder repeats transferring the divided instructions and the single instructions from the slots of the pre-decoder and the slots of the pre-decoder buffer to the main decoder as much as possible in order.