Instruction Dispatch Circuitry for Offline Storage Management
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Solution Overview
Problem
Existing processing apparatuses face inefficiencies due to the storage of both eligible and ineligible instructions in the issue circuitry, leading to increased power consumption and storage requirements.
Innovation Solution
The apparatus employs dispatch circuitry to identify linear chains of instructions based on inter-instruction dependencies, where the sequentially first instruction is dispatched to the issue circuitry, and further instructions are temporarily stored in offline storage until a chain trigger signal is received, indicating that the preceding instruction has satisfied a predefined issuing condition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If both eligible and ineligible instructions are stored in the issue circuitry, then all instructions can be managed in a single storage location, but storage requirements and power consumption increase
Solution Approach 1:
The patent divides the instruction storage system into two separate segments: issue circuitry for eligible instructions and offline storage for ineligible instructions. This segmentation reduces the storage burden on the issue circuitry while maintaining a unified management approach through the dispatch circuitry that coordinates both segments.
Solution Approach 2:
The patent extracts ineligible instructions from the issue circuitry and places them in offline storage. This extraction removes the harmful factor (excessive storage requirements and power consumption) while preserving the essential function of instruction management through the dispatch circuitry's coordination mechanism.
2Device complexity
If both eligible and ineligible instructions are stored in the issue circuitry, then storage management is simplified, but power consumption increases
Solution Approach 1:
The patent extracts ineligible instructions from the power-consuming issue circuitry and stores them in offline storage. This eliminates unnecessary power consumption while maintaining simplified management through the dispatch circuitry that tracks instruction eligibility and triggers re-insertion when appropriate.
Solution Approach 2:
The patent implements periodic checking of instruction eligibility through the chain trigger signal mechanism. When a previously ineligible instruction becomes eligible, the system periodically detects this change and re-inserts the instruction into the issue circuitry, enabling efficient power management while maintaining correct operation.
3Device complexity
If ineligible instructions are kept in issue circuitry, then instruction dispatch is simplified, but processing efficiency decreases
Solution Approach 1:
The patent segments instructions into eligible and ineligible categories, placing them in different storage locations. This segmentation improves processing efficiency by preventing ineligible instructions from blocking issue circuitry resources, while the dispatch circuitry maintains simplified coordination through unified management of both segments.
Solution Approach 2:
The patent performs preliminary classification of instructions into linear chains and identifies ineligible instructions before they enter the issue circuitry. This preliminary action prevents inefficient storage usage and improves processing efficiency, while the dispatch circuitry's chain trigger mechanism ensures smooth transition when instructions become eligible.
Data Source
AI summary
Apparatuses, methods, systems, chip containing products, and computer readable media are disclosed. An apparatus comprises dispatch circuitry to receive instructions, and to identify linear chains of instructions each comprising a first instruction and one or more further instructions, which are temporarily ineligible for execution due to a dependence on an immediately preceding instruction. The apparatus further comprises offline storage circuitry. The dispatch circuitry is configured, for each of the linear chains: to dispatch the sequentially first instruction to the issue circuitry and to retain the one or more further instructions in the offline storage circuitry until a chain trigger signal is received, the chain trigger signal indicating that a previously dispatched instruction, on which a sequentially next instruction depends, has satisfied a predefined issuing condition. In response to receipt of the chain trigger signal, the dispatch circuitry is configured to dispatch the sequentially next instruction to the issue circuitry.