Instruction Encoding Space Segmentation for Parallel Processing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Wide-issue processors require increased hardware and memory resources for parallel instruction execution, leading to higher memory footprints due to the need for extended instruction sets and larger encoding spaces, which can be inefficient in terms of memory usage.

Innovation Solution

The system employs two separate instruction sets, one encoded in a smaller space for program flow instructions and another in a larger space for data processing instructions, allowing for orthogonal execution of multiple data processing instructions in parallel without overloading the primary encoding space, thereby reducing memory usage and increasing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If an extended instruction set is used to enable parallel execution of multiple data processing instructions, then processing capability and productivity are improved, but memory footprint and encoding space requirements increase

Engineering Contradiction:
Improveparallel execution capabilityVSAvoidmemory footprint
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The instruction set is segmented into two distinct sets: a first instruction set for program flow instructions and a second instruction set for data processing instructions. This segmentation allows each instruction set to be optimized independently, with the second set enabling parallel execution while the first set maintains compact encoding, thus resolving the contradiction between parallel processing capability and memory footprint.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different encoding schemes are applied locally to different instruction types. The first instruction set uses a compact encoding scheme suitable for program flow, while the second instruction set uses an extended encoding scheme optimized for parallel data processing. This local differentiation allows the system to achieve high productivity where needed without unnecessarily increasing overall memory footprint.

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If a uniform enlarged encoding space is used for all instructions, then the instruction set can accommodate more operations and operands, but memory usage efficiency decreases

Engineering Contradiction:
Improveinstruction set coverageVSAvoidmemory usage efficiency
Core Design Contradiction:
Adaptability or versatilityVSLoss of energy

Solution Approach 1:

Instead of applying a uniform enlarged encoding space to all instructions, the patent applies different encoding schemes locally: a compact encoding for program flow instructions and an enlarged encoding for data processing instructions. This local quality approach ensures that encoding space is expanded only where necessary, maintaining adaptability for complex operations while preserving memory usage efficiency for simpler instructions.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The instruction set is divided into two segments with different encoding requirements. By segmenting the instruction space and applying appropriate encoding to each segment, the system achieves high adaptability for data processing operations without unnecessarily increasing memory usage across the entire instruction set.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9672042B2Processing system and method of instruction set encoding space utilization
Publication Date: 2017.06.06 NXP USA INC
  • US9672042B2 patent drawing
  • US9672042B2 patent drawing
  • US9672042B2 patent drawing

AI summary

A processing system comprises a processing device; a first instruction set encoded in a first encoding space and comprising one or more first instructions; a second instruction set encoded in a second encoding space different from the first encoding space and comprising two or more orthogonal second instructions; and an instruction encoder arranged to encode and encapsulate subsets of the second instructions in instruction containers, each instruction container sized to comprise a plurality of the second instructions.