Instruction Execution Circuit Dual Memory Power Reduction
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Solution Overview
Problem
Instruction execution circuits in electronic devices that handle digital sound data face high power consumption due to prolonged latency times during decoding, especially when dealing with varying data frame sizes, leading to inefficient energy usage in devices like portable music players and IC recorders.
Innovation Solution
The implementation of a dual-memory system where loop processing instructions are stored in a register with lower power consumption, allowing only the register to be accessed during repetitive 'NOP' and 'JUMP WAIT' executions, thereby reducing overall power usage without halting the clock generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processor repeatedly executes NOP and JUMP WAIT instructions during latency time, then the processor can wait for reproduction completion, but power consumption increases due to continuous memory access
Solution Approach 1:
The patent segments the program storage into two distinct memory elements: a first memory element storing the main program and a second memory element storing loop processing instructions. This segmentation allows the system to access only the small second memory element during latency periods, avoiding continuous access to the larger first memory element and thereby reducing power consumption while maintaining processing correctness.
Solution Approach 2:
The patent implements partial action by storing only the essential loop processing instructions (NOP and JUMP WAIT) in the second memory element rather than the entire program. This partial storage is sufficient to handle latency waiting, eliminating unnecessary memory access operations and reducing power consumption during idle periods.
2Manufacturing precision
If the processor waits for reproduction completion before next decoding, then data processing accuracy is maintained, but latency time increases causing inefficient energy usage
Solution Approach 1:
The patent applies preliminary action by pre-storing the loop processing instructions in the second memory element before they are needed. This allows the processor to immediately execute the waiting loop without accessing the main memory during latency periods, thereby reducing latency time while maintaining data processing accuracy through proper synchronization.
3Ease of operation
If the processor accesses the first memory element continuously, then all instructions can be retrieved, but power consumption increases during loop processing
Solution Approach 1:
The patent extracts the frequently accessed loop processing instructions from the first memory element and places them in the smaller second memory element. This extraction eliminates the need for continuous access to the power-hungry first memory element during loop execution, significantly reducing power consumption while maintaining ease of instruction retrieval for the critical waiting operations.
Data Source
AI summary
An instruction execution circuit includes: a memory circuit including a first memory element and a second memory element configured to require less power than the first memory element; a processor; and an address decoder configured to output an enable signal to either one, storing an instruction, of the first memory element and the second memory element when an address is outputted from the processor, the enable signal corresponding to a signal to output the instruction stored at the address, one portion of a program stored in the first memory element corresponding to a portion in which processing other than loop processing is described, the loop processing causing the processor to execute the specific instruction in a repetitive manner, the other portion of a program stored in the second memory element corresponding to a portion in which the loop processing is described.