16-bit and 32-bit Instruction Coexistence in Fetch Packet
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Designers of programmable data processors face challenges with 'code bloat' due to large memory requirements for 32-bit instructions, and existing data processor modes introduce overhead and complexity when mixing different instruction sizes.
Innovation Solution
Implementing a 16-bit instruction set that coexists with 32-bit instructions in the same fetch packet, using a special fetch packet header to signal and interpret 16-bit instructions, thereby expanding the opcode space and allowing for more instructions without mode switching overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If 32-bit instructions are used, then the instruction set can specify three data registers and provide complete signaling and control functions, but the memory required to store instructions becomes very large
Solution Approach 1:
The instruction set is segmented into two distinct formats: 32-bit full-featured instructions and 16-bit compressed instructions. Each format serves specific purposes, with the 16-bit format handling commonly used operations that don't require all 32-bit capabilities, thereby reducing overall code size while maintaining functionality where needed
Solution Approach 2:
Different instruction formats are applied locally based on the specific operation requirements. The 16-bit format is used for frequently executed instructions with simpler requirements, while 32-bit format is used when full functionality is needed, optimizing the balance between code size and instruction capability
2Quantity of substance
If data processor modes are used to enable shorter instructions, then alternative short length instructions can be accessed, but tracking the current mode and ensuring appropriate instructions introduces significant overhead
Solution Approach 1:
The mode switching mechanism is extracted and replaced with a more efficient format discrimination approach. Instead of using separate modes that require tracking and switching overhead, the system directly uses format identification bits within the instruction stream itself to distinguish between 16-bit and 32-bit instructions, eliminating the overhead while maintaining the ability to use both instruction lengths
Solution Approach 2:
A format identification field acts as an intermediary between the instruction stream and the execution pipeline. This intermediary field automatically indicates the instruction length without requiring mode tracking, allowing the system to seamlessly handle mixed 16-bit and 32-bit instructions without the complexity of mode management
3Quantity of substance
If shorter 16-bit instructions are used, then code size is reduced, but the opcode space is limited and cannot encode all possible signaling and control functions
Solution Approach 1:
The instruction encoding is made dynamic through the use of extension fields. The 16-bit base format provides compact encoding for common operations, while optional extension fields can be appended to provide additional functionality when needed, allowing the system to adapt the instruction size and capability dynamically based on the specific operation requirements
Solution Approach 2:
The instruction format uses a nested structure where a 16-bit core instruction can contain or be extended by additional fields. This nesting allows the basic 16-bit format to maintain compact size while providing the ability to access extended functionality through nested extension fields, effectively combining the benefits of both short and long instructions
Data Source
AI summary
This invention employs a 16-bit instruction set that has a subset of the functionality of the 32-bit instruction set. In this invention 16-bit instructions and 32-bit instructions can coexist in the same fetch packet. In the prior architecture 32-bit instructions may not span a 32-bit boundary. The 16-bit instruction set is implemented with a special fetch packet header that signals whether the fetch packet includes some 16-bit instructions. This fetch packet header also has special bits that tell the hardware how to interpret a particular 16-bit instruction. These bits essentially allow overlays on the whole or part of the 16-bit instruction space. This makes the opcode space larger permitting more instructions than with a pure 16-bit opcode space.