Instruction Fetch Pipeline Synchronization for Stale TLB Prevention
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Solution Overview
Problem
Conventional processor-based devices face disruptions and increased latency due to the need for remote processors to halt execution, flush their instruction pipelines, and restart when receiving a TLB invalidate request to prevent the use of stale TLB entries.
Innovation Solution
The implementation of instruction fetch pipeline synchronization (IFPS) in processor-based devices, where a remote processor receives a TLBI request and an IFPS request from an issuing processor, ensuring that all instructions using stale translations are processed and then the fetch pipeline is synchronized without halting execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If remote processors halt execution and flush instruction pipelines upon receiving TLBI requests, then stale TLB entries are prevented from being used, but processor performance deteriorates and latency increases
Solution Approach 1:
The instruction pipeline is segmented into multiple stages (fetch, decode, execute, etc.). The patent applies synchronization only to the fetch stage where instructions are retrieved using TLB translations, while allowing other stages to continue processing without interruption. This selective segmentation enables stale entry prevention without halting the entire processor execution flow.
Solution Approach 2:
The system performs preliminary invalidation of TLB entries in remote processors before the issuing processor needs to ensure consistency. By proactively invalidating entries and tracking their status, the system prevents stale usage without requiring remote processors to halt execution, thus maintaining performance while ensuring reliability.
2Reliability
If remote processors flush their instruction pipelines in response to TLBI requests, then address translation consistency is maintained, but execution time increases
Solution Approach 1:
The patent applies different quality levels of synchronization to different parts of the processor system. Remote processors perform lightweight local validation of TLB entry validity rather than complete pipeline flushing. This local quality approach maintains address translation consistency while minimizing the time loss associated with full pipeline flushes and restarts.
3Reliability
If remote processors restart execution after flushing pipelines, then stale translations are eliminated, but system efficiency decreases
Solution Approach 1:
The patent implements a feedback mechanism where the issuing processor tracks the status of TLBI requests sent to remote processors. Remote processors provide feedback about their synchronization status without requiring full pipeline flushes. This feedback loop enables the system to eliminate stale translations reliably while maintaining high system efficiency by avoiding unnecessary execution restarts.
Data Source
AI summary
Performing instruction fetch pipeline synchronization (IFPS) in processor-based devices is disclosed herein. In some exemplary aspects, a processor-based device provides multiple processors including a remote processor. The remote processor receives, from an issuing processor, a translation lookaside buffer (TLB) invalidation (TLBI) request indicating a request to invalidate an address translation, and subsequently receives an IFPS request from the issuing processor. The remote processor determines that any previously received TLBI requests including the most recent TLBI request have completed. Upon receiving the IFPS request, the remote processor determines that all instructions within a fetch pipeline portion that were potentially fetched using address translations older than the IFPS request have proceeded from the fetch pipeline portion of an instruction processing circuit to an execution pipeline portion of the instruction processing circuit. The remote processor then performs a data synchronization barrier (DSB) operation, and issues a synchronization acknowledgement to the issuing processor.