Instruction Fusion for Processor Pipeline Efficiency
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Solution Overview
Problem
Current data processing systems face inefficiencies due to dependencies between instructions, which limit the execution rate of instructions in processor pipelines.
Innovation Solution
A data processing apparatus and method that detects parent and child instructions with a destination register dependency, adjusts the child instruction to be logically equivalent to the execution of both, allowing for potential execution in a single processor cycle by modifying the instruction stream and managing register availability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If instructions are executed in sequence with dependencies, then correctness is maintained, but instruction execution rate is limited
Solution Approach 1:
The patent merges a parent instruction and its dependent child instruction into a single fused instruction that performs both operations sequentially. This eliminates the dependency barrier between instructions, allowing the fused instruction to be executed independently and in parallel with other instructions, thereby increasing the instruction execution rate without compromising correctness
Solution Approach 2:
The detection circuitry segments the instruction stream into parent-child instruction pairs that can be fused. By identifying and separating these fusible instruction pairs from the overall instruction flow, the system can selectively fuse compatible instructions while maintaining the integrity of the original program logic
2Productivity
If instructions are executed in parallel, then execution rate increases, but dependency correctness may be compromised
Solution Approach 1:
The detection circuitry performs preliminary analysis of the instruction stream to identify parent-child instruction pairs with destination-source register dependencies. By detecting these relationships before execution and fusing them into a single instruction unit, the system preserves the required execution order while enabling parallel execution of the fused instruction with other independent instructions
Solution Approach 2:
By merging the parent and child instructions into a single fused instruction, the patent eliminates the dependency relationship that would otherwise prevent parallel execution. The fused instruction encapsulates both operations with their correct sequential logic, allowing it to be treated as an atomic unit that can execute in parallel with other independent instructions without compromising correctness
Data Source
AI summary
A data processing apparatus includes detection circuitry that detects a parent instruction and a child instruction from a stream of instructions. The parent instruction references a destination register that is referenced as a source register by the child instruction. Adjustment circuitry then adjusts the child instruction to produce an adjusted child instruction whose behaviour is logically equivalent to a behaviour of executing the parent instruction followed by the child instruction.