Instruction Fusion Preprocessing for Cross-Fetch-Group Execution
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Solution Overview
Problem
Existing data processing systems face inefficiencies in executing fused instructions due to limitations in fusing operations, particularly when instructions are not available within the same fetch group, leading to missed opportunities for increased processing efficiency.
Innovation Solution
The system incorporates upstream and downstream instruction fusing circuitry to detect fusible instructions across multiple pipeline stages, associating fusion category indicators, and selectively fusing instructions from different fetch groups to generate fused instructions for execution by coprocessors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If instructions are fused only within the same fetch group, then the fusing operation is simple and fast, but the number of fusible instructions is limited and processing efficiency is reduced
Solution Approach 1:
The patent extends instruction fusing from a single-fetch-group dimension to multiple fetch groups by introducing cross-fetch-group fusing capability. The fusing circuitry now operates across temporal and instructional boundaries, allowing instructions from different fetch groups to be combined into fused instructions, thereby increasing the pool of fusible instructions without being constrained by fetch group boundaries.
Solution Approach 2:
The system performs preliminary detection of fusible instructions across multiple fetch groups before execution. The fusing circuitry identifies candidate instructions in advance and prepares fused instructions for subsequent execution, enabling optimization opportunities to be captured without impacting real-time execution performance.
2Productivity
If fused instructions are communicated to coprocessors, then execution throughput is improved, but compatibility issues arise when coprocessors cannot execute certain fused instruction categories
Solution Approach 1:
The patent implements category-specific handling of fused instructions based on coprocessor capabilities. Each coprocessor is associated with data defining specific categories of fused instructions it can execute. The system selectively routes appropriate fused instruction categories to compatible coprocessors, allowing each component to operate within its optimal capability range while maintaining overall system versatility.
Solution Approach 2:
The system dynamically adjusts instruction routing based on coprocessor capability parameters. By changing the parameter of instruction category assignment according to each coprocessor's execution capabilities, the system ensures that fused instructions are directed to appropriate processing units, thereby maintaining compatibility while maximizing throughput.
3Productivity
If more instructions are fused together, then processing efficiency increases, but the risk of execution errors and compatibility issues increases
Solution Approach 1:
The patent applies partial fusing by generating fused instructions that combine a subset of fusible instructions rather than fusing all possible instructions together. This selective approach maintains execution reliability by keeping fused instruction groups at manageable sizes while still achieving efficiency gains through fusion of compatible instructions.
Solution Approach 2:
The system incorporates feedback mechanisms to monitor fused instruction execution and detect potential errors. By observing execution outcomes and adjusting fusing operations accordingly, the system maintains reliability while maximizing processing efficiency through intelligent fusion management.
Data Source
AI summary
Apparatus comprises communication circuitry to receive instructions including fused instructions communicated by further circuitry; processing circuitry to execute instructions; and fused instruction pre-processing circuitry to selectively process a given fused instruction received from the communication circuitry and representing a fusion of n individual instructions, where n is an integer greater than 1, so as to generate m separate instructions for execution by the processing circuitry, where m is an integer greater than one and less than or equal to n.