Instruction Generation Unit for Specialized Processor Translation
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Solution Overview
Problem
The development of specialized processor designs is hindered by the high degree of integration between the processor and its instruction set architecture, making it expensive and time-consuming to create or revise an instruction set, as well as the need for extensive verification and modification of associated development tools.
Innovation Solution
An instruction generation unit interfaces a host computer to a specialized processor, converting host-program operation codes and operands into decoded instructions suitable for execution by the specialized processor, using an object class library and custom functional units to generate custom instructions without requiring detailed knowledge of the processor's architecture, allowing for efficient processing of visual data sets through a tile-processor architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a new instruction set is created for a specialized processor, then the processor can be optimized for specific applications, but the development cost and time increase significantly due to the need for extensive verification and modification of associated development tools
Solution Approach 1:
The patent introduces an instruction generation unit (IGU) as an intermediary component between the host processor and the specialized processor. The IGU contains a decoder that translates host processor instructions into specialized processor instructions, and an instruction buffer that manages the instruction stream. This intermediary handles the complexity of instruction set translation, allowing the specialized processor to be optimized for specific applications without requiring extensive modification of the complete development toolchain.
Solution Approach 2:
The system separates the instruction processing functionality into distinct segments: the host processor maintains its native instruction set for general-purpose programming, while the specialized processor focuses on optimized execution of translated instructions. The IGU acts as a bridge that segments the instruction translation and buffering tasks from the core processing functions, allowing each component to be optimized independently.
2Productivity
If host processor instructions are directly executed on a specialized processor with a different instruction set, then processing efficiency improves, but the need for extensive instruction set translation and toolchain modification increases development complexity
Solution Approach 1:
The instruction generation unit serves as an intermediary that handles instruction set translation between the host processor and specialized processor. The decoder within the IGU translates host instructions into specialized processor instructions, while the instruction buffer manages the translation process and instruction streaming. This intermediary approach enables processing efficiency gains from specialized hardware without requiring the host compiler and toolchain to be extensively modified.
Solution Approach 2:
The system creates a virtual representation of the host processor instruction set within the IGU's decoder. Rather than requiring the host processor to physically execute on the specialized hardware, the decoder copies and translates the instruction semantics into the target instruction set, allowing efficient execution on specialized hardware while maintaining compatibility with standard host programming models.
Data Source
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AI summary
Methods, devices and systems are disclosed that interface a host computer to a specialized processor. In an embodiment, an instruction generation unit comprises attribute, decode, and instruction buffer stages. The attribute stage is configured to receive a host- program operation code and a virtual host-program operand from the host computer and to expand the virtual host-program operand into an operand descriptor. The decode stage is configured to receive the first operand descriptor and the host-program operation code, convert the host-program operation code to one or more decoded instructions for execution by the specialized processor, and allocate storage locations for use by the specialized processor. The instruction buffer stage is configured to receive the decoded instruction, place the one or more decoded instructions into one or more instruction queues, and issue decoded instructions from at least one of the one or more instruction queues for execution by the specialized processor.