Instruction Sequence Hash Tracking for Better IC Test Coverage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing testing tools and techniques for integrated circuits, such as processors, fail to capture a satisfactory percentage of errors and provide adequate coverage of the various circuits and functionalities during random instruction sequence testing.
Innovation Solution
Implementing an apparatus with execution circuitry to execute instruction sequences, hash value calculation circuitry to calculate hash values based on data register elements, and control circuitry to manage hash value calculations, ensuring errors persist through test runs by storing hash values in a register.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If random instruction sequence testing is used to test integrated circuits, then testing coverage is improved, but error detection accuracy deteriorates due to result dilution
Solution Approach 1:
The patent applies preliminary action by calculating hash values of instruction sequences before execution and storing them in registers. This preliminary hashing action allows the system to track and preserve error information throughout the random instruction sequence testing, preventing result dilution while maintaining comprehensive testing coverage.
Solution Approach 2:
The patent implements feedback by continuously calculating hash values of executed instructions and comparing them with expected results. The hash calculation circuitry provides feedback about instruction execution accuracy, enabling the system to detect errors in real-time during random instruction sequence testing without sacrificing testing coverage.
2Measurement precision
If hash value calculation circuitry is added to track errors, then error detection accuracy is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the hash value calculation circuitry to serve multiple functions: it calculates hash values for error tracking, stores results in registers for later comparison, and integrates with the existing instruction execution pipeline. This multi-functionality reduces the need for separate dedicated error tracking circuits, thereby limiting the increase in device complexity.
Solution Approach 2:
The patent merges the error tracking functionality with the existing instruction execution and register file structures. The hash value calculation circuitry is integrated into the pipeline, utilizing existing registers and memory structures to store and compare hash values, thereby minimizing additional hardware complexity while achieving accurate error detection.
Data Source
AI summary
The present disclosure relates generally to integrated circuits and relates more particularly to circuits, systems, and/or processes for instruction sequence test error tracking.