Instruction Loop Cache Bitwise Tag Comparison

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Solution Overview

Problem

Microprocessors face inefficiencies in power consumption and processing speed due to the time and energy required to fetch instructions from external memory, particularly in applications where innermost loops dominate execution time.

Innovation Solution

A microprocessor with an instruction loop cache that includes a cache array and tag storage, which determines cache hits or misses through bitwise comparison, allowing for efficient caching and reduced power consumption by storing and retrieving instructions within the cache array when possible.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If instructions are fetched from external memory, then the microprocessor can execute instructions, but power consumption increases and processing speed decreases

Engineering Contradiction:

Improveprocessing speedVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent segments the instruction storage into two parts: a small, fast instruction loop cache for frequently executed loop instructions, and external memory for other instructions. This segmentation allows the system to optimize access to the most frequently accessed instructions while maintaining overall storage capacity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by providing specialized fast access storage (instruction loop cache) specifically for loop instructions, which have different access patterns compared to other instructions. The cache is optimized with tag storage and bitwise comparison mechanisms to quickly identify and retrieve loop instructions.

Inventive Principle:

Principle #3Local quality

2Productivity

If a full instruction cache is implemented, then all instructions can be cached, but device complexity and power consumption increase

Engineering Contradiction:

Improveinstruction fetching efficiencyVSAvoidcache structure complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent extracts only the most frequently accessed loop instructions from the general instruction stream and places them in a dedicated instruction loop cache. This extraction approach focuses caching resources on the subset of instructions that provide the greatest performance benefit, avoiding the complexity of caching all instructions.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent uses preliminary action by implementing a tag storage mechanism that pre-computes and stores tag values for loop instructions. When a loop instruction is detected, its tag is stored in advance, enabling rapid identification and caching of subsequent loop iterations without complex real-time analysis.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS9183155B2Microprocessor and method for using an instruction loop cache thereof

Publication Date: 2015.11.10 ANDES TECH

AI summary

A microprocessor is provided, which includes a processor core and an instruction loop cache. The processor core provides a fetch address of an instruction stream. The fetch address includes a tag and an index. The instruction loop cache receives the fetch address from the processor core. The instruction loop cache includes a cache array and a tag storage. The cache array stores multiple cache entries. Each cache entry includes a tag identification (ID). The cache array outputs the tag ID of the cache entry indicated by the index of the fetch address. The tag storage stores multiple tag values and output the tag value indicated by the tag ID output by the cache array. The instruction loop cache determines whether a cache hit or a cache miss occurs based on a bitwise comparison between the tag of the fetch address and the tag value output by the tag storage.