Microprocessor Instruction Masking for Fault Attack Detection
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Solution Overview
Problem
Existing methods for executing machine code are vulnerable to fault attacks, which can compromise the integrity of instructions and disrupt the operation of microprocessors, making it difficult to detect compromisations such as skipped or replaced instructions, especially when they occur during decoding.
Innovation Solution
The method involves constructing and using masks to unmask instructions in a microprocessor pipeline, allowing for the detection of execution faults and compromisations by comparing the expected and actual masks, and triggering countermeasures such as signaling an execution fault.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If fault attacks are applied to disrupt microprocessor operation, then information about machine code or unexpected behavior can be obtained, but the integrity and security of the system is compromised
Solution Approach 1:
The patent applies preliminary action by pre-computing and storing expected mask values for all possible instruction sequences before execution. During runtime, the actual masks are compared against these pre-computed expected masks to detect any deviations caused by fault attacks, thereby preventing information leakage while maintaining system security.
Solution Approach 2:
The patent implements feedback by continuously monitoring the masks generated during instruction execution and comparing them against expected values. When a discrepancy is detected, the system triggers an interrupt or error handling mechanism, creating a closed-loop security verification system that actively responds to potential fault attacks.
2Productivity
If traditional execution methods are used, then processing speed is maintained, but the system is vulnerable to skipped or replaced instructions during decoding
Solution Approach 1:
The patent introduces masks as an intermediary verification layer between the instruction decoder and the execution units. These masks are generated based on the expected instruction sequence and used to verify the actual decoded instructions, enabling detection of skipped or replaced instructions without significantly impacting processing speed.
Solution Approach 2:
The patent segments the instruction verification process into distinct stages: mask generation, mask comparison, and error handling. This segmentation allows the security verification to be performed in parallel with instruction execution, maintaining processing speed while ensuring reliability through systematic verification at each stage.
3Reliability
If masks are constructed and compared for every instruction, then detection of compromisation is enabled, but computational overhead and processing time increase
Solution Approach 1:
The patent reduces processing time by pre-computing expected mask values during a compilation or initialization phase, storing them in lookup tables. During actual execution, only simple comparison operations are needed rather than full mask computation, significantly reducing the time overhead while maintaining comprehensive detection capability.
Solution Approach 2:
The patent optimizes the mask representation and comparison parameters to enable faster verification. By using compact mask formats and efficient comparison algorithms, the system achieves high-speed verification that minimally impacts overall processing throughput while maintaining reliable detection of instruction compromisation.
Data Source
AI summary
A method for executing a machine code using a microprocessor includes, after an operation of decoding a current loaded instruction, constructing a mask from the signals generated by an instruction decoder in response to decoding of the current loaded instruction by the decoder. The constructed mask varies as a function of the current loaded instruction. Subsequently, before an operation of decoding a next loaded instruction, the next loaded instruction is unmasked using the constructed mask.