Instruction Paging in Reconfigurable Fabric via Circular Buffers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional computing systems face limitations in flexibility and cost-effectiveness, as custom ASICs are inflexible and costly to reconfigure, while FPGAs offer versatility but are slow and time-consuming to reconfigure, failing to meet the demands for fast and complex semiconductor implementations.
Innovation Solution
The implementation of instruction paging using circular buffers that allow for quick reconfiguration of processing elements by swapping instructions between memory and buffers, enabling asynchronous operation and dynamic reprogramming without retiming or additional clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional microprocessors are used, then high functional diversity is achieved, but processing speed and reconfigurability are limited
Solution Approach 1:
The patent implements dynamic reconfiguration by allowing the circular buffer to be updated with new instruction sets during operation. The buffer can be rewritten with different instructions to change the functionality of the reconfigurable fabric on-the-fly, enabling the system to adapt between different computational tasks without physical reconfiguration or extensive redesign.
2Speed
If custom ASICs are used, then processing speed is improved, but flexibility and reconfigurability are lost
Solution Approach 1:
The patent segments the instruction storage into a circular buffer that can be independently updated. This segmentation allows the processing fabric to maintain its high-speed ASIC-like operation while the instruction buffer can be reconfigured separately to change functionality, thus achieving both speed and flexibility simultaneously.
3Adaptability or versatility
If FPGAs are used, then reconfigurability is achieved, but reconfiguration time is excessive
Solution Approach 1:
The patent prepares multiple instruction sets in advance in the circular buffer, allowing the reconfigurable fabric to switch between pre-computed instruction sets without real-time computation overhead. This preliminary preparation of instruction sequences enables rapid task switching without the extensive reconfiguration time characteristic of FPGAs.
4Adaptability or versatility
If reconfigurable devices are used, then configuration flexibility is improved, but instruction bandwidth is limited
Solution Approach 1:
The circular buffer architecture enables continuous instruction delivery to the reconfigurable fabric without interruption. The buffer maintains a steady stream of instructions, ensuring that the processing elements are continuously utilized without idle cycles waiting for reconfiguration or instruction delivery, thus maximizing instruction bandwidth while maintaining flexibility.
Data Source
AI summary
Circular buffers containing instructions that enable the execution of operations on logical elements are described where data in the circular buffers is swapped to storage. Data stored in circular buffers is paged in and out to a second level memory. State information for each logical element is also saved and restored using paging memory. Logical elements such as processing elements are provided instructions via circular buffers. The instructions enable a group of processing elements to perform operations implementing a desired functionality. That functionality is changed by updating the circular buffers with new instructions that are transferred from paging memory. The previous instructions can be saved off in paging memory before the new instructions are copied over to the circular buffers. This enables the hardware to be rapidly reconfigured amongst multiple functions.