Instruction Perturbation for Device Security
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Solution Overview
Problem
Existing systems lack effective methods to securely process executable instructions, making them vulnerable to code reuse attacks that exploit the predictable order of instructions.
Innovation Solution
The proposed solution involves perturbing executable instructions by randomly or pseudo-randomly modifying their order, ensuring that each instruction corresponds to a valid slot in the memory hierarchy, thereby thwarting code reuse attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If executable instructions are processed in a predictable order, then system performance and execution efficiency are improved, but device security deteriorates due to vulnerability to code reuse attacks
Solution Approach 1:
The system dynamically randomizes the execution order of independent instructions within an instruction packet at runtime. The processor manager shuffles instructions based on validity checks and slot rules, creating a dynamic execution sequence that varies between executions. This resolves the contradiction by maintaining high execution efficiency through parallel processing while improving security through unpredictable instruction ordering that prevents code reuse attacks.
Solution Approach 2:
The system changes the execution parameter of instruction order from fixed to randomized. By implementing randomization logic that shuffles instruction sequences within packets and validates slot compatibility, the system transforms the static execution model into a dynamic one. This maintains productivity through efficient parallel execution while enhancing security by making the execution pattern unpredictable to attackers.
2Reliability
If the order of executable instructions is randomized to improve security, then device security is improved, but system complexity increases due to additional validation requirements
Solution Approach 1:
The system performs preliminary validation by pre-establishing slot rules and checking instruction validity before execution. The processor manager validates that shuffled instructions comply with slot constraints and architectural requirements in advance. This preliminary action reduces the complexity burden during runtime by preparing validation criteria beforehand, allowing secure randomization without excessive processing overhead.
Solution Approach 2:
The system introduces an intermediary processor manager that handles the complexity of instruction randomization and validation. This intermediary component sits between the instruction packet and the execution units, managing the shuffling logic, slot rule validation, and coordination. By isolating the complexity in a dedicated intermediary layer, the overall system complexity is managed more effectively while maintaining security enhancements.
3Reliability
If instructions are shuffled within instruction packets, then code reuse attack resistance is improved, but instruction processing time increases due to additional shuffling operations
Solution Approach 1:
The system applies partial randomization by shuffling only independent instructions within each instruction packet rather than all instructions globally. The processor manager identifies and shuffles independent instructions that can be executed in any order, while maintaining the relative order of dependent instructions. This partial action provides sufficient security improvement by disrupting predictable patterns, while minimizing processing time overhead by limiting the scope of shuffling operations.
Data Source
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AI summary
Methods, systems, and devices for techniques for instruction perturbation for improved device security are described. A device may assign a set of executable instructions to an instruction packet based on a parameter associated with the instruction packet, and each executable instruction of the set of executable instructions may be independent from other executable instructions of the set of executable instructions. The device may select an order of the set of executable instructions based on a slot instruction rule associated with the device, and each executable instruction of the set of executable instructions may correspond to a respective slot associated with memory of the device. The device may modify the order of the set of executable instructions in a memory hierarchy post pre-decode based on the slot instruction rule and process the set of executable instructions of the instruction packet based on the modified order.