Instruction Pointer Patching for Hardware-Assisted Control Flow Integrity
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Solution Overview
Problem
Existing control flow integrity (CFI) validation techniques require source code modification and/or binary re-instrumentation, incur performance penalties, and provide limited accuracy, making them inefficient against code reuse attacks like ROP, JOP, and COP.
Innovation Solution
A hardware-assisted control flow directed graph (CFDG) monitoring system that uses CPU telemetry to learn and enforce legitimate control flow paths, detecting and preventing invalid transfers in real-time across various computing environments, including bare metal, virtual machines, and containers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing CFI validation techniques are used, then control flow integrity is validated, but source code modification and binary re-instrumentation are required, increasing device complexity
Solution Approach 1:
The patent replaces software-based CFI validation mechanisms (source code modification, binary re-instrumentation) with a hardware-based solution. The processor includes dedicated hardware circuits that automatically monitor control flow transfers and validate them against stored legitimate target addresses, eliminating the need for software-level modifications while maintaining CFI validation functionality.
2Reliability
If existing CFI validation techniques are used, then control flow validation is provided, but performance penalties are incurred
Solution Approach 1:
The system performs preliminary action by pre-storing legitimate control flow target addresses in a dedicated hardware data structure during system initialization or code loading. This pre-computation and pre-storage of valid targets allows the hardware monitor to perform rapid O(1) validation of control flow transfers during runtime, avoiding the performance overhead of dynamic analysis or software-based validation.
3Reliability
If existing CFI validation techniques are used, then some control flow validation is provided, but accuracy is limited
Solution Approach 1:
The patent introduces a hardware intermediary component that sits between the control flow transfer mechanism and the execution pipeline. This hardware monitor intercepts control flow transfers, compares them against pre-stored legitimate targets in a dedicated data structure, and blocks invalid transfers before they can execute, providing more accurate and comprehensive validation than software-based approaches.
4Measurement precision
If hardware-assisted CFDG monitoring is implemented, then detection accuracy is improved, but device complexity increases
Solution Approach 1:
The hardware monitoring system is segmented into distinct functional modules: a control flow transfer detection unit that identifies control flow changes, a data structure storage unit that holds pre-computed legitimate targets, and a validation unit that compares actual transfers against stored targets. This modular segmentation allows each component to perform its function efficiently while keeping the overall system manageable and maintainable.
Data Source
AI summary
Techniques and systems described herein relate to monitoring executions of computer instructions on computing devices based on learning and generating a control flow directed graph. The techniques and systems include determining a learned control flow directed graph for a program and subsequently determining valid target destinations for transitions within the program. The instructions of the program may be executed by determining a destination for a transition, performing the transition when the destination is included in the list of valid target destinations, and performing a secondary action when the destination is not included in the list of valid target destinations.