Instruction Prefetch Throttling via Branch Prediction Count
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Solution Overview
Problem
High power consumption in data processing systems due to unnecessary instruction cache lookups for speculative instructions that are later discarded, particularly in high-performance processors where branch prediction circuitry is distant from the instruction cache, leading to wasted power in fetching and discarding instructions.
Innovation Solution
Implementing throttle prediction circuitry that maintains a count of instructions between branch instructions predicted as taken, allowing the fetch circuitry to operate in a throttled mode, limiting further cache accesses for a predetermined number of clock cycles based on this count, thereby reducing unnecessary cache lookups and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If branch prediction circuitry is placed close to the instruction cache to enable same-cycle prediction, then instruction fetch speed is improved, but power consumption increases significantly
Solution Approach 1:
The system segments the prediction process into two phases: a lightweight same-cycle prediction stage that provides immediate guidance, and a more accurate multi-cycle prediction stage that refines the prediction. This segmentation allows the system to benefit from fast initial predictions while avoiding the full power cost of continuous high-accuracy prediction at the cache interface.
Solution Approach 2:
The system performs preliminary branch prediction using simplified logic in the same clock cycle as instruction fetch, providing early guidance to the fetch unit. This preliminary action reduces the need for subsequent speculative fetches, thereby reducing overall power consumption while maintaining acceptable fetch speed.
2Productivity
If speculative instructions are fetched continuously to keep execution pipeline full, then productivity is improved, but power consumption increases due to unnecessary cache lookups
Solution Approach 1:
The system uses feedback from branch prediction outcomes and instruction flow analysis to dynamically control the fetch unit. When a taken branch is predicted, the feedback mechanism suppresses further speculative fetches, preventing wasted cache lookups. This feedback-based control maintains productivity by ensuring the pipeline remains full when appropriate while reducing power consumption by eliminating unnecessary fetch operations.
Solution Approach 2:
Instead of continuously fetching instructions, the system applies partial fetching by limiting speculative instruction fetches to only when needed based on branch prediction outcomes. This partial action approach maintains sufficient instruction throughput while significantly reducing the number of unnecessary cache lookups and associated power consumption.
3Use of energy by moving object
If branch prediction is performed several pipeline stages after fetch to reduce power, then power consumption is reduced, but instruction fetch accuracy decreases leading to more discarded speculative instructions
Solution Approach 1:
The prediction process is segmented into a fast same-cycle prediction component and a slower multi-cycle refinement component. The same-cycle prediction provides immediate (though less accurate) guidance to reduce speculative fetches, while the multi-cycle component improves accuracy over time. This segmentation balances power consumption and prediction accuracy by using the appropriate level of prediction at each stage.
Solution Approach 2:
A preliminary prediction is performed in the same clock cycle as instruction fetch, providing early guidance even if less accurate. This preliminary action reduces the number of speculative fetches immediately, and subsequent more accurate predictions further refine the process, achieving a balance between power savings and prediction reliability.
Data Source
AI summary
A sequence of buffered instructions includes branch instructions. Branch prediction circuitry predicts if each branch instruction will result in a taken branch when executed. Normally, the fetch circuitry retrieves speculative instructions between the time that a source branch instruction is retrieved and the prediction if that source branch instruction will result in the taken branch. If the source branch instruction is predicted as taken, then the speculative instructions are discarded, and a count value indicates a number of instructions in the sequence between that source branch instruction and a subsequent branch instruction in the sequence that is also predicted as taken. Responsive to a subsequent occurrence of the source branch instruction predicted as taken, a throttled mode limits the number of instructions subsequently retrieved dependent on the count value, and then any further instructions are not retrieved for a number of clock cycles.