Instruction Pre-Sending Tables for Low-Latency Memory Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current sophisticated prefetching techniques in computer architectures require intimate knowledge of processor microarchitecture events, making them difficult and costly to implement and less efficient.
Innovation Solution
A system for pre-sending memory blocks to higher levels of the memory hierarchy using a high-level representation of memory block usage, allowing for efficient pre-sending without precise knowledge of processor microarchitectural events, guided by a table linking program instructions and their associated memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sophisticated prefetching techniques are used to track program execution paths and predict future memory blocks, then prefetching accuracy is improved, but device complexity and implementation cost increase significantly
Solution Approach 1:
The patent performs preliminary analysis of program execution paths and memory block usage patterns before actual execution. By pre-computing and storing the relationship between instruction addresses and memory blocks in a table during program loading or initial execution, the system prepares prefetching information in advance without requiring complex real-time analysis during processor operation.
Solution Approach 2:
The patent introduces an intermediary table structure that stores pre-analyzed relationships between instruction addresses and memory blocks. This table acts as a mediator between the processor and the memory hierarchy, providing prefetching information without requiring the processor or cache controller to perform complex microarchitectural analysis. The table simplifies the prefetching decision process by providing ready-made mappings.
2Loss of time
If prefetching is performed closer to processor execution to improve timing accuracy, then latency is reduced, but the system requires more precise knowledge of microarchitectural events which increases complexity
Solution Approach 1:
The system performs preliminary setup of the prefetching table during program loading or initial execution phases, storing the relationships between instruction addresses and memory blocks in advance. This allows the prefetching mechanism to operate with simple address matching during actual execution without requiring complex real-time microarchitectural event tracking, thus reducing latency while maintaining simplicity.
3Ease of manufacture
If basic sequential prefetching is used to fetch next address-sequential blocks, then implementation simplicity is maintained, but prefetching effectiveness and productivity decrease
Solution Approach 1:
The patent performs preliminary analysis of program execution paths and memory block usage patterns before actual execution. By pre-computing and storing the relationship between instruction addresses and memory blocks in a table during program loading or initial execution, the system prepares prefetching information in advance without requiring complex real-time analysis during processor operation.
Solution Approach 2:
The patent introduces an intermediary table structure that stores pre-analyzed relationships between instruction addresses and memory blocks. This table acts as a mediator between the processor and the memory hierarchy, providing prefetching information without requiring the processor or cache controller to perform complex microarchitectural analysis. The table simplifies the prefetching decision process by providing ready-made mappings.
Data Source
AI summary
A computer architecture provides a pre-sending of memory blocks from a lower level memory hierarchy component to a higher level memory hierarchy component using a table linking a set of memory blocks holding instructions that are executed in different fragments of a program. The table is used to pre-send memory blocks to the higher level memory hierarchy component in anticipation of their use by a processor executing the program.