Instruction Read Buffer for Processor Cache Miss Reduction
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Solution Overview
Problem
The existing cache structures face bottlenecks due to cache misses, particularly in multi-category misses, which hinder performance improvement in modern processors, and existing solutions like multi-way set-associative caches are limited by power consumption and speed restrictions.
Innovation Solution
An instruction cache system that includes an instruction read buffer (IRB) which autonomously outputs instructions to the processor core, utilizing a token passer mechanism for parallel execution of instructions, dependency checking, and proactive filling of the IRB with branch target instructions to prevent cache misses and reduce tag matching in critical paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-way set-associative cache is used to reduce conflict miss, then cache hit rate is improved, but power consumption increases and speed decreases
Solution Approach 1:
The cache system is segmented into two independent parts: a traditional multi-way set-associative cache for data storage and an instruction read buffer (IRB) for instruction supply. The IRB is further divided into multiple banks that can be independently accessed. This segmentation allows the power-intensive tag matching operations to be isolated from the instruction reading path, enabling the IRB to operate with lower power consumption while maintaining high instruction hit rate through its own hit detection mechanism.
Solution Approach 2:
The instruction read buffer (IRB) acts as an intermediary component between the instruction cache and the processor core. It proactively reads instructions from the cache and stores them in its banks, mediating the data flow and reducing the need for frequent cache accesses. This intermediary structure allows the system to benefit from both the high capacity of the cache and the low power consumption of the IRB during instruction execution.
2Reliability
If multi-way set-associative cache is used to reduce conflict miss, then cache hit rate is improved, but access speed decreases
Solution Approach 1:
The cache system is segmented into two independent parts: a traditional multi-way set-associative cache for data storage and an instruction read buffer (IRB) for instruction supply. The IRB is further divided into multiple banks that can be independently accessed. This segmentation allows the power-intensive tag matching operations to be isolated from the instruction reading path, enabling the IRB to operate with lower power consumption while maintaining high instruction hit rate through its own hit detection mechanism.
Solution Approach 2:
The instruction read buffer proactively reads instructions from the cache in advance and stores them in its banks before they are needed by the processor core. This preliminary action reduces the access latency by having instructions ready in the IRB when the core needs them, effectively speeding up the instruction supply process while maintaining the benefits of the multi-way cache structure.
3Device complexity
If traditional cache structure is used, then implementation is simple, but cache misses occur frequently hindering performance
Solution Approach 1:
The system merges a traditional multi-way set-associative cache with an instruction read buffer (IRB) that has proactive reading capabilities. The cache and IRB work together as a unified instruction storage and supply system, combining the high capacity and associativity of the cache with the proactive prefetching and low-latency access of the IRB. This merging resolves the contradiction by maintaining simple implementation of the traditional cache while adding the performance benefits of proactive reading through the IRB.
Data Source
AI summary
This invention provides a cache system and method based on instruction read buffer (IRB). When applied to the field of processor, it is capable of filling instructions to the instruction read buffer which can be directly accessed by processor core and the processor core outputs instruction to the processor core for execution autonomously and achieve a high cache hit rate.