Instruction Scheduling for Reconfigurable Array Processors
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Solution Overview
Problem
Existing instruction scheduling methods for reconfigurable array processors are complex and require significant hardware knowledge, with multiple stages reducing designability and affecting performance due to complexity and dependency on each stage's scheduling.
Innovation Solution
An instruction scheduling method and system that determines the fan-out of vertices in a data flow graph, establishes retiming inequalities, introduces registers to align vertices with processing units, and uses a maximum clique algorithm to distribute instructions efficiently, ensuring optimal scheduling and resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple stages are used in instruction scheduling, then scheduling completeness is improved, but device complexity and design difficulty increase
Solution Approach 1:
The scheduling algorithm is divided into multiple independent stages: resource allocation stage, retiming stage, and scheduling stage. Each stage handles a specific aspect of the scheduling problem independently, allowing the system to achieve complete scheduling coverage while maintaining manageable complexity at each individual stage.
Solution Approach 2:
The patent introduces intermediate data structures and algorithms that bridge different scheduling stages. These intermediaries facilitate smooth transitions between stages without requiring complex integration logic, thereby maintaining scheduling completeness while reducing overall design complexity.
2Reliability
If multiple stages are used in instruction scheduling, then scheduling coverage is improved, but ease of operation deteriorates
Solution Approach 1:
By segmenting the scheduling process into distinct stages with clear interfaces, the patent makes the overall complex system easier to operate. Each stage can be designed, tested, and modified independently, improving designability while maintaining comprehensive scheduling coverage.
Solution Approach 2:
The patent creates universal interface standards and data structures that work across all scheduling stages. This multi-functionality allows the same framework to handle different scheduling scenarios without requiring custom integration logic for each case, thereby improving ease of operation.
3Adaptability or versatility
If fan-out constraints are enforced, then hardware compatibility is improved, but productivity may be affected
Solution Approach 1:
The patent implements dynamic fan-out management where the effective fan-out constraint is adjusted based on the current scheduling state and available hardware resources. This dynamic approach maintains hardware compatibility while minimizing the impact on scheduling efficiency by allowing more flexible resource utilization when conditions permit.
Solution Approach 2:
The patent transforms the fixed fan-out constraint into a variable parameter that can be optimized during the scheduling process. By changing the effective fan-out parameter based on retiming values and resource availability, the system maintains hardware compatibility while improving overall scheduling productivity.
Data Source
AI summary
An instruction scheduling method and an instruction scheduling system for a reconfigurable array processor. The method includes: determining whether a fan-out of a vertex in a data flow graph (DFG) is less than an actual interconnection number of a processing unit in a reconfigurable array; establishing a corresponding relationship between the vertex and a correlation operator of the processing unit; introducing a register to a directed edge, acquiring a retiming value of each vertex; arranging instructions in such a manner that retiming values of the instruction vertexes are in ascending order, and acquiring transmission time and scheduling order of the instructions; folding the DFG, placing an instruction to an instruction vertex; inserting a register and acquiring a current DFG; and acquiring a common maximum subset of the current DFG and the reconfigurable array by a maximum clique algorithm, and distributing the instructions.