Instruction Scheduling via Topological Sorting for Parallel Computing
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Solution Overview
Problem
Traditional CPU platforms are inadequate for handling the increasing computing demands of complex neural networks, necessitating the use of heterogeneous computing platforms like FPGAs, GPUs, or ASICs, but these platforms face inefficiencies due to high data access times compared to parallel execution times, requiring optimization of instruction scheduling to enhance computing efficiency.
Innovation Solution
A high parallelism computing system and instruction scheduling method that constructs a directed acyclic graph to determine a reasonable instruction execution order, avoiding deadlocks by topologically sorting instructions based on dependencies, and using a dependency matrix to distribute instructions efficiently across function modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional CPU platforms are used for neural network computation, then programming simplicity is maintained, but computing efficiency deteriorates due to inability to handle increasing computational scale and complexity
Solution Approach 1:
The computing system is segmented into multiple independent function modules (data loading engine, data operation engine, data storage engine) that can execute instructions in parallel. Each module operates independently on specific tasks, enabling concurrent processing and improving overall computing efficiency while maintaining modular simplicity
Solution Approach 2:
The system performs preliminary actions by pre-loading data into the internal buffer before computation is needed. The data loading engine proactively fetches required data from external memory, ensuring that computation engines have data ready when needed, thereby reducing waiting time and improving throughput
2Productivity
If heterogeneous computing platforms (FPGAs, GPUs, ASICs) are used, then computing efficiency is improved, but data access time increases relative to parallel execution time
Solution Approach 1:
The data loading engine performs preliminary data loading into the internal buffer before computation begins. By pre-fetching data and storing it in the buffer, the system eliminates data access bottlenecks during parallel computation, as all function modules can read from the buffer without waiting for external memory access
Solution Approach 2:
The system maintains continuous useful action by keeping multiple function modules actively executing instructions in parallel. The data loading, operation, and storage engines operate concurrently on different data elements, ensuring that the computing pipeline remains full and efficient without idle waiting periods
3Productivity
If parallel execution is implemented, then computing efficiency is improved, but deadlock risks increase due to instruction dependencies
Solution Approach 1:
The system performs preliminary action by topologically sorting all instructions before execution begins. This pre-ordering ensures that instructions are executed in a valid sequence that respects all dependencies, preventing circular wait conditions and deadlocks from occurring during parallel execution
Solution Approach 2:
The system implements feedback mechanisms where function modules signal completion of their tasks, and the instruction reading and distribution module uses this feedback to manage the execution queue. This feedback loop ensures that dependencies are properly tracked and resolved, preventing deadlock conditions
4Productivity
If instruction scheduling is optimized, then computing efficiency is improved, but system resource consumption increases
Solution Approach 1:
The system segments instructions into distinct types (data loading, data operation, data storage) and assigns them to dedicated function modules. This segmentation allows for specialized processing and efficient resource utilization, as each module handles only its specific task type, reducing overall resource consumption while maintaining high throughput
Data Source
AI summary
A high parallelism computing system and instruction scheduling method thereof are disclosed. The computing system comprises: an instruction reading and distribution module for reading a plurality of types of instructions in a specific order, and distributing the acquired instructions to corresponding function modules according to the types; an internal buffer for buffering data and instructions for performing computation; a plurality of function modules each of which sequentially executes instructions of the present type distributed by the instruction reading and distribution module and reads the data from the internal buffer; and wherein the specific order is obtained by topologically sorting the instructions according to a directed acyclic graph consisting of the types and dependency relationships. By reading the instructions based on the topological sorting the directed acyclic graph constructed according to the types and dependency relationships, the deadlock caused by the instruction dependencies can be avoided by a relatively simple operation.