Arithmetic Processing Apparatus Instruction Selection Circuit
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Solution Overview
Problem
Arithmetic processing apparatus performance is degraded due to limitations in the number of entries and issue ports in reservation stations, which increase operation latency and reduce processing capacity, especially when trying to execute instructions with varying dependencies and priorities.
Innovation Solution
The apparatus includes an instruction execution control circuit with an executable instruction information storage circuit, a priority information storage circuit, and an output determination circuit that selectively issues instructions based on executable and priority information, allowing for efficient selection and execution of instructions with reduced logical stages and increased queue entries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of entries in the reservation station queue is increased to improve processing capacity, then more instructions can be buffered and executed out-of-order, but the time required to select an instruction and check dependencies increases, causing operation latency to increase
Solution Approach 1:
The patent segments the instruction selection process by implementing separate selection circuits for different instruction types (e.g., integer instructions, floating-point instructions, load/store instructions). Each segment handles a specific category of instructions independently, allowing parallel selection operations that reduce the overall time required to select instructions from a large queue, thus resolving the contradiction between increased processing capacity and operation latency
Solution Approach 2:
The patent introduces a new dimension to the selection process by implementing a hierarchical selection structure with multiple levels of selection circuits. The first level performs coarse-grained selection based on instruction type and readiness, while subsequent levels perform fine-grained selection. This multi-dimensional approach allows the system to efficiently manage large numbers of queue entries without proportionally increasing selection latency
2Productivity
If the number of issue ports is increased to improve processing capacity, then more instructions can be executed simultaneously, but the logic operations required for instruction selection increase, causing selection time to increase
Solution Approach 1:
The patent segments the issue ports into specialized functional units (e.g., integer execution units, floating-point execution units, branch prediction units), each with its own dedicated selection circuit. This segmentation allows each selection circuit to be simpler and more focused, reducing the logic operations required per port while maintaining high overall processing capacity through parallel operation of multiple specialized ports
Solution Approach 2:
The patent implements universal selection circuits that can handle multiple instruction types through configurable selection logic. These circuits use control signals to adapt their selection criteria based on the current instruction mix, allowing the same hardware structure to serve multiple functions and reducing the need for separate complex selection logic for each issue port
3Productivity
If the number of issue ports is increased to improve processing capacity, then more instructions can be executed simultaneously, but the time required to check dependencies increases, causing operation latency to increase
Solution Approach 1:
The patent performs preliminary dependency checking by maintaining dependency information in the queue entries themselves and performing initial dependency validation when instructions are enqueued. This preliminary action ensures that when instructions reach the selection stage, much of the dependency checking has already been done, allowing rapid selection even with multiple issue ports and reducing the overall operation latency
Solution Approach 2:
The patent introduces dependency tags and readiness flags as intermediary data structures that mediate between the large queue and the multiple issue ports. These intermediaries encode dependency relationships in a compact form that can be rapidly evaluated by selection circuits, enabling efficient dependency checking across multiple parallel issue ports without proportionally increasing selection time
Data Source
AI summary
An arithmetic processing apparatus includes an instruction execution control circuit that outputs an instruction from an entry of entries, including an executable instruction information storage circuit storing executable instruction information indicating whether an instruction in each of the entries is executable, a priority information storage circuit including, for each entry, storage areas storing priority information indicating whether an instruction in an entry has higher priority on an entry-by-entry basis, an executable instruction information write circuit writing the executable instruction information in response to determining whether an instruction in each of the entries is executable, a priority information write circuit writing the priority information in response to determining whether an instruction in each of the entries has higher priority, and an output determination circuit selecting an entry from which an instruction is output on a basis of the executable instruction information and the priority information.