Instruction Size Register for Kernel Event Skip Handling
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Solution Overview
Problem
Processor circuits face inefficiencies due to underutilization of hardware resources when executing instructions of varying sizes, as they often encounter processing events that require transferring control to a kernel, making it difficult to determine and skip the size of the violating instruction, especially when memory is executable-only and non-readable.
Innovation Solution
A processor circuit is equipped with an event handler circuit that stores program counter, cause, and size information of the violating instruction in register circuits, allowing the processor to skip the violating instruction by incrementing the program counter based on the stored size information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If instructions of different sizes are executed in a processor circuit, then the processor can handle diverse instruction formats, but hardware resources are underutilized due to inefficiencies in determining and skipping violating instruction sizes
Solution Approach 1:
The patent applies preliminary action by storing the size of the current instruction in a register circuit before executing the instruction. This allows the processor to have the instruction size information readily available when a processing event occurs, enabling efficient determination of whether to skip the instruction without re-analyzing the instruction size at that point.
Solution Approach 2:
The patent introduces an intermediary mechanism (register circuit) that stores instruction size information. This intermediary component bridges the gap between instruction fetching and execution, providing the necessary size information to the event handler circuit when processing events occur, thus resolving the efficiency problem without requiring complex analysis at the point of event handling.
2Reliability
If memory is set to executable-only and non-readable, then security is improved by preventing reading of instructions, but it becomes difficult to determine the size of the violating instruction
Solution Approach 1:
The patent applies preliminary action by capturing and storing the instruction size information in a register circuit before the memory's executable-only restriction prevents reading. This ensures that the size information is preserved and available for event handling without requiring actual reading of the instruction from the restricted memory.
Solution Approach 2:
The patent uses copying by creating a copy of the instruction size information and storing it in a register circuit. This copy serves as a surrogate for the actual instruction, providing the necessary size information without requiring access to the original instruction in the protected memory, thus maintaining security while enabling detection.
3Reliability
If the processor transfers control to a kernel upon encountering a processing event, then system control is improved, but resource utilization decreases due to the overhead of control transfer and instruction size determination
Solution Approach 1:
The patent applies preliminary action by pre-storing the instruction size in a register circuit before the processing event occurs. When the event happens and control needs to be transferred to the kernel, the size information is already available, eliminating the need for additional analysis during the critical event handling phase and reducing the overhead associated with control transfer.
Data Source
AI summary
A processor circuit that includes a plurality of register circuits and an event handler circuit is disclosed. The event handler circuit may detect a processing event that causes the processor circuit to halt execution of a current instruction and transfer control to a kernel. In response to a detection of the processing event, the event handler circuit may store a program counter value corresponding to the current instruction, information indicative of a cause of the processing event, and a size of the current instruction in corresponding register circuits of the plurality of register circuits.