Extending Data RAM Capacity Using Unused Instruction SRAM
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Solution Overview
Problem
Modified Harvard Architecture processors face a performance penalty due to the need to access external DRAM when the on-chip data RAM capacity is exhausted, as accessing external DRAM is significantly slower than using on-chip SRAM.
Innovation Solution
Utilizing available space in the on-chip instruction RAM to store data structures, strategically selecting candidates based on alignment and access patterns to minimize performance impact, and optimizing data placement to extend the data RAM capacity without incurring the high costs of external memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If external DRAM is used to extend data storage capacity, then data storage capacity is improved, but access speed deteriorates
Solution Approach 1:
The patent merges the instruction RAM and data RAM address spaces, allowing the instruction RAM to serve dual purposes: storing instructions and extending data storage capacity. This consolidation enables the processor to utilize existing on-chip instruction RAM resources for data storage, thereby extending effective data RAM capacity without requiring additional external DRAM accesses.
Solution Approach 2:
The instruction RAM is given multi-functionality by allowing it to be accessed for both instruction fetches and data load/store operations. The modified Harvard architecture enables the same physical memory resource (instruction RAM) to fulfill multiple functions: code storage and data storage, eliminating the need to rely solely on external DRAM for data extension.
2Quantity of substance
If instruction RAM is used to store data, then data storage capacity is improved, but instruction execution speed may deteriorate
Solution Approach 1:
The system dynamically manages the instruction RAM by allowing flexible allocation between instructions and data based on runtime needs. The architecture supports dynamic switching between instruction access and data access modes, enabling the processor to adaptively utilize available instruction RAM space for data storage when not fully occupied by instructions, thereby optimizing both storage capacity and execution speed.
Solution Approach 2:
The patent changes the addressing parameters and access modes of the instruction RAM to enable dual functionality. By modifying how the instruction RAM is addressed and accessed (allowing data bus access in addition to instruction bus access), the system transforms a single-purpose memory into a multi-purpose resource without requiring hardware redesign.
3Speed
If on-chip data RAM capacity is increased, then access speed is improved, but device complexity increases
Solution Approach 1:
The system utilizes existing on-chip instruction RAM resources to provide data storage functionality, eliminating the need for additional external DRAM interfaces and controllers. By making the instruction RAM serve data storage needs, the architecture reduces device complexity while maintaining fast on-chip access speeds, as no new external memory subsystem is introduced.
Data Source
AI summary
On-chip instruction RAM is leveraged as an extension of on-chip data RAM during normal use of a modified Harvard Architecture processor. Unused space in an instruction RAM is detected in a modified Harvard Architecture processor. During operation of the processor this unused space is used to load and store data normally loaded and stored in an on-chip data RAM. A performance penalty associated with swapping out to external memory is reduced. The type of data stored in the unused portion of the instruction RAM may be selected to optimize performance. In one implementation, the unused space in the instruction RAM is used to load and store only a single type of data, such as heap, stack, initialized or uninitialized data.