Instruction Translation Circuit Advanced Microcode Execution
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Solution Overview
Problem
Conventional processors implementing the x86 architecture face inefficiencies in executing complex instructions due to the time-consuming translation process, which leads to reduced processor performance and increased idleness.
Innovation Solution
An instruction translation circuit with a first and second instruction translator, along with an instruction detection circuit, allows for the advanced translation of parts of formatted macro instructions with set trap bits, enabling the processor to accelerate instruction execution by translating complex parts ahead of time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the microcode translator waits for the instruction translator to complete translation before performing translation, then translation accuracy is ensured, but processor executing efficiency deteriorates
Solution Approach 1:
The patent applies preliminary action by having the instruction detection circuit identify complex instructions with set trap bits and initiate advanced translation by the second instruction translator before the first instruction translator completes its translation. This allows the microcode translator to start working on translation tasks in advance, overlapping translation operations to reduce total execution time while maintaining accuracy through proper sequencing of translation results.
2Device complexity
If complex instructions are translated sequentially by a single translator, then device complexity is reduced, but translation time increases
Solution Approach 1:
The patent segments the translation function into two distinct translators: a first instruction translator for initial translation and a second instruction translator for advanced translation of complex instructions. The instruction detection circuit identifies which instructions require advanced translation. This segmentation allows parallel processing of translation tasks, reducing overall translation time while maintaining manageable device complexity through functional division.
Solution Approach 2:
The second instruction translator performs advanced translation in advance for complex instructions identified by the instruction detection circuit. This preliminary action overlaps translation operations, allowing the system to prepare translation results before they are strictly needed, thereby reducing the critical path translation time without requiring a completely complex rearchitecture.
3Speed
If the processor translates all instructions immediately, then instruction execution speed is maximized, but processor idleness increases
Solution Approach 1:
The system performs preliminary translation actions only for complex instructions with set trap bits identified by the instruction detection circuit, rather than translating all instructions immediately. This selective advanced translation accelerates execution of complex instructions that would otherwise cause processor idleness, while simpler instructions proceed through the normal translation path, optimizing the balance between execution speed and resource utilization.
Data Source
AI summary
An instruction translation circuit, a processor circuit, and an executing method thereof are provided. The instruction translation circuit is adapted for being disposed in the processor circuit. The instruction translation circuit includes a formatted instruction queue, a first instruction translator, an instruction detection circuit, and a second instruction translator. The formatted instruction queue stores a plurality of formatted macro instructions. The first instruction translator translates a first formatted macro instruction of the formatted macro instructions and outputs a first micro instruction. When the instruction detection circuit determines that a trap bit in the first formatted macro instruction is set and a part of the first formatted macro instruction can be translated in advance, the instruction detection circuit outputs first trap information. The second instruction translator translates the part of the first formatted macro instruction in advance according to the first trap information to output a second micro instruction.