Instruction Translator for x86 ARM Microinstruction Generation

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Solution Overview

Problem

Computing device manufacturers face challenges in developing systems that can efficiently run both x86 and ARM architecture programs due to the need for separate hardware and software support, leading to potential wasted investments when one architecture becomes dominant over the other.

Innovation Solution

A microprocessor with an instruction set architecture that translates x86 and ARM instructions into microinstructions, allowing the execution pipeline to handle both architectures, enabling the microprocessor to run both x86 and ARM machine language programs by using a hardware instruction translator and execution pipeline.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a microprocessor supports both x86 and ARM architectures through hardware translation, then versatility is improved, but device complexity increases

Engineering Contradiction:

Improveability to run both x86 and ARM programsVSAvoidhardware translation mechanism

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The microprocessor is designed with a universal execution pipeline that can execute instructions from both x86 and ARM architectures through a common hardware translation mechanism. The instruction translator converts both architecture types into a unified microinstruction set, allowing a single hardware platform to support multiple instruction set architectures without requiring separate execution paths for each architecture.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

An instruction translator serves as an intermediary component between the external instruction set (x86 or ARM) and the internal execution pipeline. This translator layer abstracts the architectural differences and presents a standardized microinstruction interface to the execution units, enabling the complex task of supporting multiple architectures through a single translation layer rather than direct hardware implementation of each architecture.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If separate hardware support is provided for x86 and ARM architectures, then reliability is improved, but manufacturing cost increases

Engineering Contradiction:

Improveperformance consistencyVSAvoidmanufacturing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The execution pipeline merges the execution paths for x86 and ARM architectures into a single unified structure. Both architecture types share common execution units, data paths, and control logic after the translation stage. This consolidation eliminates the need for duplicate hardware components that would be required if separate execution paths were implemented for each architecture, thereby reducing manufacturing costs while maintaining performance consistency through the shared execution infrastructure.

Inventive Principle:

Principle #5Merging (Combining)

3Device complexity

If software translation methods are used, then device complexity is reduced, but productivity decreases

Engineering Contradiction:

Improvehardware translation mechanismVSAvoidexecution speed

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The patent replaces software-based translation mechanisms with a hardware implementation of the instruction translator. This hardware translator operates at the same speed as the execution pipeline, enabling parallel translation and execution without the performance penalties associated with software interpretation. The hardware translation mechanism processes instructions in the same clock cycle as execution, eliminating the sequential bottleneck inherent in software translation while maintaining the architectural abstraction benefits.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS9128701B2Generating constant for microinstructions from modified immediate field during instruction translation

Publication Date: 2015.09.08 VIA TECH INC

AI summary

An ISA-defined instruction includes an immediate field having a first and second portions specifying first and second values, which instructs the microprocessor to perform an operation using a constant value as one of its source operands. The constant value is the first value rotated/shifted by a number of bits based on the second value. An instruction translator translates the instruction into one or more microinstructions. An execution pipeline executes the microinstructions generated by the instruction translator. The instruction translator, rather than the execution pipeline, generates the constant value for the execution pipeline as a source operand of at least one of the microinstructions for execution by the execution pipeline. Alternatively, if the immediate field value is not within a predetermined subset of values known by the instruction translator, the instruction translator generates, rather than the constant, a second microinstruction for execution by the execution pipeline to generate the constant.