Insulated Bump Bonding for Semiconductor Power Chips
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Solution Overview
Problem
The fabrication of semiconductor power devices requires extensive processing to eliminate series resistance, leading to increased costs due to the need for metal deposition on both sides and backside contact processing, which complicates current distribution and manufacturing.
Innovation Solution
The use of bump bonding and a thicker lead-frame with an insulating layer and solder connections simplifies current distribution by eliminating the need for backside contact processing and intricate lead-frames, allowing for flip-chip assembly with reduced processing steps and lower manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal deposition is performed on both front and back sides to achieve adequate current handling, then current carrying capability is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent inverts the conventional approach by performing metal deposition only on the front side of the semiconductor die, then flipping the die to bond it to the lead frame. This eliminates the need for back side metal deposition and extensive substrate resistance elimination processing, while still achieving adequate current handling through the flipped configuration.
Solution Approach 2:
The patent applies preliminary action by depositing all necessary metal conductors on the front side of the die before flipping it. The metal layers are prepared in advance with proper thickness and configuration to handle current after the flip, eliminating the need for subsequent back side processing.
2Reliability
If back side contact processing is used to eliminate series resistance, then electrical performance is improved, but manufacturing cost increases
Solution Approach 1:
Instead of processing the back side to eliminate series resistance, the patent flips the die after front side metal deposition. The series resistance issue is eliminated by the inverted configuration where the metal layers on the front side serve as the primary current path after bonding to the lead frame.
3Reliability
If extensive processing steps are used to achieve low contact resistance, then connection quality is improved, but manufacturing productivity decreases
Solution Approach 1:
All necessary metal deposition and patterning is performed as preliminary action on the front side before flipping. This consolidates multiple processing steps into a single sequence performed before the flip, eliminating subsequent processing steps and improving manufacturing productivity.
Solution Approach 2:
The flip operation itself becomes a key step that eliminates the need for extensive back side processing. By inverting the die, the patent achieves low contact resistance through the front side metal configuration rather than through extensive back side processing.
4Reliability
If intricate lead-frames are used to distribute current, then current distribution is improved, but device complexity increases
Solution Approach 1:
The patent performs preliminary action by depositing the metal conductor patterns directly on the front side of the die in the desired configuration. This eliminates the need for intricate lead-frame structures to achieve current distribution, as the metal layers themselves provide the necessary current paths.
Solution Approach 2:
The patent moves the current distribution function from the lead-frame dimension to the die surface dimension. By depositing metal conductors directly on the die surface in appropriate patterns, current distribution is achieved in the planar dimension rather than requiring complex three-dimensional lead-frame structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs, achieves lower connection resistance, and enables a smaller form-factor for semiconductor power devices, allowing for wafer-level-chip-scale-package solutions and interconnection of multiple power-FETs in a single package.
Implementation Method 1
connecting material disposed within each opening; and a lead-frame comprising gate, source and drain lead-fingers placed on top of the die and connected with the plurality of contact elements of the gate, source and drain via the connecting material
Data Source
AI summary
A semiconductor power chip, may have a semiconductor die having a power device fabricated on a substrate thereof, wherein the power device has at least one first contact element, a plurality of second contact elements and a plurality of third contact elements arranged on top of the semiconductor die; and an insulation layer disposed on top of the semiconductor die and being patterned to provide openings to access the plurality of second and third contact elements and the at least one first contact element.