Insulated-Gate Transistor Layout for ON Resistance and Active Clamp
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Solution Overview
Problem
Semiconductor devices with insulation gate-type transistors face a trade-off between achieving low ON resistance and excellent active clamp capability, as increasing the channel area reduces ON resistance but worsens active clamp capability due to temperature rise, while reducing the channel area improves active clamp capability but increases ON resistance.
Innovation Solution
The semiconductor device incorporates two insulation gate-type transistors and a control circuit/wiring to manage current flow, allowing separate control of these transistors in normal and active clamp operations, optimizing channel utilization rates to achieve low ON resistance and effective active clamp capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the area of channel is increased, then the ON resistance can be reduced, but the active clamp capability is reduced due to sharp temperature rise
Solution Approach 1:
The patent divides the single transistor channel into two separate channels (first channel and second channel) with different area sizes. The first transistor has a first area and the second transistor has a second area, where at least one area is different between the two transistors. This segmentation allows each transistor to handle different current loads, with the larger transistor handling normal operation current and the smaller transistor handling active clamp current, thereby reducing overall temperature rise while maintaining low ON resistance.
2Temperature
If the area of channel is reduced, then the active clamp capability can be improved, but the ON resistance is increased
Solution Approach 1:
The patent segments the current handling function into two transistors with different channel areas. The first transistor with the larger area provides low ON resistance for normal operation, while the second transistor with the smaller area provides improved active clamp capability with reduced temperature rise. Both transistors work together to satisfy both requirements that would be contradictory in a single transistor design.
Solution Approach 2:
The patent changes the parameter of channel area by creating two transistors with different area values. By setting at least one transistor to have a different area from the other, the system can optimize the balance between ON resistance and active clamp capability, allowing each transistor to operate in its optimal performance range for different operational modes.
Data Source
AI summary
A semiconductor device includes a semiconductor layer, an insulation gate-type first transistor which is formed in the semiconductor layer, an insulation gate-type second transistor which is formed in the semiconductor layer, and a control wiring which is formed on the semiconductor layer such as to be electrically connected to the first transistor and the second transistor, and transmits control signals that control the first transistor and the second transistor to be in ON states in a normal operation and that control the first transistor to be in an OFF state and the second transistor to be in an ON state in an active clamp operation.