Insulated Gate Semiconductor Device With Floating Layer And Hole Stopper
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Solution Overview
Problem
Conventional insulated gate semiconductor devices face challenges in reducing switching loss, conduction loss, and noise while maintaining breakdown resistance, particularly due to the trade-off between carrier accumulation effect and breakdown resistance when increasing impurity concentration in the hole stopper layer.
Innovation Solution
The design incorporates a trench structure with a floating layer having a lower impurity concentration than the channel layer, where the hole stopper layer is partially spaced from the gate insulation layer, allowing for enhanced breakdown resistance and reduced switching loss by controlling the thickness of the gate insulation layer to adjust the threshold voltage of the MOSFET and IGBT.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the impurity concentration in the hole stopper layer is increased to enhance the carrier accumulation effect, then the switching loss and noise are reduced, but the breakdown resistance deteriorates
Solution Approach 1:
The base layer is divided into two regions with different impurity concentrations: a first base layer region with higher impurity concentration to enhance carrier accumulation and reduce switching loss, and a second base layer region with lower impurity concentration to maintain breakdown resistance. This local differentiation allows each region to optimize for its specific function.
Solution Approach 2:
The base layer is segmented into multiple regions by trenches, creating distinct functional zones. The first base layer region contains emitter regions for carrier injection, while the second base layer region serves as a floating layer for charge storage. This segmentation enables independent optimization of each region's impurity concentration.
2Loss of energy
If the impurity concentration in the hole stopper layer is increased to improve the carrier accumulation effect, then the conduction loss is reduced, but the breakdown resistance deteriorates
Solution Approach 1:
The first base layer region with higher impurity concentration improves carrier accumulation to reduce conduction loss, while the second base layer region with lower impurity concentration preserves breakdown resistance. Each region's local properties are optimized for its specific role in the device operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces switching loss and noise while maintaining high breakdown resistance by optimizing the impurity concentration and placement of the hole stopper layer, enhancing the carrier discharging capability and improving the overall performance of the IGBT.
Implementation Method 1
a floating effect in the other semiconductor region is enhanced by increasing an impurity concentration in the hole stopper layer so that a carrier accumulation effect of the IGBT element can be increased
Implementation Method 2
a gate insulation layer formed on a surface of the trench, a gate electrode formed on the gate insulation layer in the trench
Data Source
AI summary
An insulated gate semiconductor device includes a first conductivity-type semiconductor substrate, a second conductivity-type base layer on a first surface side of the substrate, a trench dividing the base layer into channel and floating layers, and a first conductivity-type emitter region that is formed in the channel layer and in contact with the trench. The semiconductor device includes a gate insulation layer in the trench, a gate electrode on the insulation layer, an emitter electrode electrically connected to the emitter region and the floating layer, a second conductivity-type collector layer in the substrate, and a collector electrode on the collector layer. The floating layer has a lower impurity concentration than the channel layer. The floating layer has a first conductivity-type hole stopper layer located at a predetermined depth from the first surface of the substrate and at least partially spaced from the insulation layer.