Insulated-Gate Semiconductor Device With Segmented Impurity Regions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional insulated-gate semiconductor devices face challenges in maintaining high reverse breakdown voltage between the source and drain due to electric field concentration at the curvature of the p+ type impurity region, which necessitates a large area p+ type impurity region that reduces the operation region and transistor cell density.
Innovation Solution
The semiconductor device features gate electrodes and channel regions formed in a stripe shape with a p+ type impurity region at the outer periphery, allowing channel regions to extend under the gate pad electrode, and a protection diode with stripe-shaped pn junction diodes connected in parallel, reducing the curvature and electric field concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large area p+ type impurity region is formed below the gate pad electrode to maintain high reverse breakdown voltage, then the reverse breakdown voltage is improved, but the operation region area is reduced
Solution Approach 1:
The p+ type impurity region is segmented into multiple discrete p+ regions arranged in a matrix pattern below the gate pad electrode, rather than forming a single large continuous region. This segmentation allows the operation region to extend into areas that would otherwise be occupied by a monolithic impurity region, thereby increasing the operation region area while still providing sufficient reverse breakdown voltage through the distributed p+ regions
Solution Approach 2:
The invention transitions from a conventional single large p+ region to a multi-dimensional matrix arrangement of multiple smaller p+ regions. This dimensional reorganization allows the impurity regions to be distributed across both lateral dimensions, effectively utilizing the space below the gate pad electrode while permitting the operation region to occupy the interstitial areas, thus resolving the area conflict
2Reliability
If transistor cells are not disposed below the gate pad electrode to form a p+ type impurity region, then the reverse breakdown voltage is maintained, but the transistor cell density is reduced
Solution Approach 1:
The invention segments the area below the gate pad electrode into multiple functional zones: discrete p+ type impurity regions for reverse breakdown protection and interstitial transistor cell regions for high-density integration. This segmentation allows transistor cells to be disposed below the gate pad electrode in the spaces between the p+ regions, thereby increasing transistor cell density while maintaining the necessary reverse breakdown voltage through the distributed p+ protection regions
3Reliability
If the curvature of the p+ type impurity region is reduced to mitigate electric field concentration, then the reverse breakdown voltage is improved, but the area of the p+ type impurity region must be increased
Solution Approach 1:
The invention segments the p+ type impurity region into multiple discrete smaller p+ regions with controlled curvature, arranged in a matrix pattern. Each individual p+ region can be designed with optimized curvature characteristics to mitigate electric field concentration, while the collective array of segmented regions provides the necessary total protection area without requiring a single large continuous region, thus avoiding the area penalty
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration secures a high reverse breakdown voltage without reducing the operation region area, allowing for increased transistor cell density and adjustable breakdown voltage by modifying the channel region settings.
Implementation Method 1
When the reverse voltage is applied between the source and the drain, depletion layers are spread from in pn junctions between the channel regions 34 and the n− type semiconductor layers 31b over the operation region 51, thereby securing the reverse breakdown voltage between the source and the drain.
Implementation Method 2
a protection diode 43d formed by doping impurities in polysilicon is disposed below the gate pad electrode 48
Data Source
AI summary
Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below the entire lower surface of the gate pad electrode. Furthermore, a protection diode is formed in polysilicon with a stripe shape below the gate pad electrode.