Insulated-Gate Semiconductor Device With Segmented Impurity Regions
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Solution Overview
Problem
Conventional insulated-gate semiconductor devices face challenges in maintaining high reverse breakdown voltage between the source and drain due to electric field concentration at the curvature of the p+ type impurity region, which hinders the efficient operation of transistor cells and increases on-resistance.
Innovation Solution
The semiconductor device incorporates gate electrodes and channel regions formed in a stripe shape with pn junction diodes extending outside the gate pad electrode, allowing channel regions to be disposed under the gate pad electrode and reducing the curvature of the p+ type impurity region, thereby mitigating electric field concentration and securing a high reverse breakdown voltage without reducing the operation region area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a p+ type impurity region is formed below the gate pad electrode to secure reverse breakdown voltage, then the reverse breakdown voltage is improved, but electric field concentration occurs at the curvature of the impurity region which deteriorates performance
Solution Approach 1:
The p+ type impurity region is divided into multiple segments: a first p+ type impurity region formed below the gate pad electrode, and a second p+ type impurity region formed in the operation region. This segmentation allows each region to have optimized dimensions and positions, reducing electric field concentration at any single location while maintaining overall reverse breakdown voltage.
Solution Approach 2:
Different regions have different impurity concentrations and geometries tailored to their specific functions. The first p+ type impurity region below the gate pad electrode has specific dimensions optimized for reverse breakdown, while the second p+ type impurity region in the operation region has dimensions optimized for reducing electric field concentration. This local optimization resolves the contradiction between achieving high breakdown voltage and avoiding field concentration.
2Productivity
If the operation region area is increased to improve device performance, then productivity is improved, but the reverse breakdown voltage becomes difficult to maintain
Solution Approach 1:
The solution moves from a single large p+ type impurity region to multiple smaller p+ type impurity regions distributed in different locations (below gate pad electrode and in operation region). This dimensional redistribution allows the operation region area to be maximized while the reverse breakdown voltage is maintained through the distributed impurity regions.
3Productivity
If transistor cells are disposed below the gate pad electrode to increase operation region, then productivity is improved, but the reverse breakdown voltage is deteriorated due to curvature effects
Solution Approach 1:
Transistor cells are permitted to be disposed below the gate pad electrode, increasing the operation region. The p+ type impurity region is segmented into multiple regions with optimized dimensions, where the second p+ type impurity region in the operation region has a width of 0.5 to 2.0 times the gate electrode width, optimizing both the operation region utilization and reverse breakdown voltage.
Solution Approach 2:
The width of the second p+ type impurity region is specifically controlled to be 0.5 to 2.0 times the gate electrode width. This parameter optimization allows transistor cells to be disposed below the gate pad electrode while maintaining adequate reverse breakdown voltage by controlling the electric field distribution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively secures a high reverse breakdown voltage between the drain and source, allowing for efficient transistor operation while maintaining the area for transistor cells, and allows for arbitrary setting of the breakdown voltage by modifying the channel region settings.
Implementation Method 1
When the reverse voltage is applied between the source and the drain, depletion layers are spread from pn junctions between the channel regions 34 and the n− type semiconductor layers 31b over the operation region 51, thereby securing the reverse breakdown voltage between the source and the drain.
Data Source
AI summary
Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below the entire lower surface of the gate pad electrode. Furthermore, a protection diode is formed in a conductive layer disposed at the outer periphery of an operation region.