Insulated Gate Semiconductor Device Two-Layer Electrode Structure
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Solution Overview
Problem
Conventional insulated gate semiconductor devices face challenges in reducing the area where no transistor cells can be formed, leading to increased on-resistance and non-uniform operation due to the overlap of protection diodes with gate pad portions, which restricts the expansion of the device region and affects the semiconductor chip's performance.
Innovation Solution
The semiconductor device incorporates a two-layer structure for the gate electrode layers, with the first layer overlapping the protection diode and the second layer forming a pad portion that does not overlap the diode, allowing transistor cells to be positioned below the gate pad portion, reducing the area where no transistors can be formed and minimizing on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the protection diode is positioned to overlap with the gate pad portion in conventional devices, then the gate pad can be formed, but the area where transistor cells cannot be formed increases, leading to increased on-resistance
Solution Approach 1:
The patent applies dimensionality change by transitioning from a two-dimensional planar layout to a three-dimensional stacked structure. The gate electrode is positioned above the protection diode in the vertical dimension, allowing both components to coexist without overlapping in the planar view. This enables the gate pad portion to be formed while minimizing the exclusion area for transistor cells, thereby increasing the device region area without increasing on-resistance.
2Ease of operation
If the gate pad portion is formed to connect to external terminals, then external connections are enabled, but the overlapping protection diode structure restricts transistor cell placement and increases the non-functional area
Solution Approach 1:
The patent resolves this contradiction by stacking the gate electrode vertically above the protection diode. This three-dimensional arrangement allows the gate pad portion to extend to the surface for external connections while the protection diode remains below, eliminating planar overlap. Consequently, transistor cells can be positioned in areas that would otherwise be excluded, maximizing the functional device region area.
3Ease of manufacture
If a conventional planar structure is used with overlapping protection diode and gate pad, then manufacturing is simpler, but the on-resistance increases due to reduced transistor cell area
Solution Approach 1:
The patent introduces vertical stacking of the gate electrode above the protection diode, transforming the conventional planar structure into a three-dimensional configuration. This approach maintains manufacturing feasibility through standard semiconductor fabrication processes while significantly increasing the device region area by eliminating unnecessary planar overlap. The result is reduced on-resistance due to the larger effective transistor cell area.
Data Source
AI summary
A two-layer electrode structure is provided. A protection diode is provided not to overlap a gate pad portion. Cells and a first one of source electrode layers can be provided below the gate pad portion, so that the differences in resistance among various points in the source electrode layers can be decreased. In addition, the protection diode is positioned adjacent to a device region and at an end portion, of a chip, outward of the device region in such a way as to be in the closest proximity to the gate pad portion. A larger device region with efficient transistor operation can thus be secured, and the resistance of the first source electrode layer below a wiring portion can be reduced.