Insulated Metal Substrate Solder Mask Removal for Adhesion

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Solution Overview

Problem

The adhesion force between the solder mask layer and the sealing member in semiconductor power module packages is weak, leading to reduced insulation breakdown voltage and insulating characteristics due to poor interface bonding.

Innovation Solution

Partly or completely removing the solder mask layer from the insulating metal substrate to expose conductive patterns, allowing a sealing member to directly contact the substrate and increase adhesion force, thereby enhancing the interface bonding between the insulating metal substrate and the sealing member.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the solder mask layer is formed on the insulating metal substrate to cover metal patterns for die soldering, then the die soldering process is enabled, but the adhesion force between the solder mask layer and the sealing member is weak

Engineering Contradiction:
Improvedie soldering capabilityVSAvoidadhesion force between solder mask layer and sealing member
Core Design Contradiction:
Ease of manufactureVSStrength

Solution Approach 1:

The solder mask layer is selectively removed from specific regions (peripheral areas where sealing member contacts the substrate) while being retained in other regions (central areas covering metal patterns). This segmentation allows the package to maintain die soldering capability where the mask layer remains, while achieving strong adhesion with the sealing member where the mask layer is removed, exposing the conductive patterns for direct contact.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the insulating metal substrate are treated differently regarding the solder mask layer presence. The peripheral regions have the solder mask layer removed to create strong adhesion zones for the sealing member, while central regions retain the solder mask layer to enable die soldering. This local differentiation resolves the contradiction by optimizing each region for its specific function.

Inventive Principle:
Principle #3Local quality

2Strength

If the solder mask layer is completely removed to maximize adhesion force with the sealing member, then the adhesion force is improved, but the die soldering capability is lost

Engineering Contradiction:
Improveadhesion force between sealing member and insulating metal substrateVSAvoiddie soldering capability
Core Design Contradiction:
StrengthVSEase of manufacture

Solution Approach 1:

The solder mask layer removal is segmented into specific peripheral regions rather than complete removal. This allows the sealing member to directly contact the conductive patterns in peripheral areas for strong adhesion, while the solder mask layer remains intact in central areas to provide the necessary surface for die soldering operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The substrate exhibits different properties in different locations: peripheral regions have exposed conductive patterns for maximum adhesion with the sealing member, while central regions retain the solder mask layer for die soldering. This local quality differentiation simultaneously achieves both strong adhesion and die soldering capability.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS7842545B2Semiconductor package having insulated metal substrate and method of fabricating the same
Publication Date: 2010.11.30 SEMICON COMPONENTS IND LLC
  • US7842545B2 patent drawing
  • US7842545B2 patent drawing
  • US7842545B2 patent drawing

AI summary

Provided is a semiconductor package in which an adhesion force between an insulation metal substrate and a molding member is increased by removing a solder mask layer from the insulation metal substrate and a method of fabricating the semiconductor package. The semiconductor package includes an insulation metal substrate that includes a base member, an insulating layer disposed on the base member, and conductive patterns formed on the insulating layer. Semiconductor chips are arranged on the conductive patterns. Solder mask patterns are arranged on the conductive patterns to surround the semiconductor chips. Leads are electrically connected to the conductive patterns through wires. A sealing member is arranged on an upper surface and side surfaces of the substrate to cover portions of the leads, the wires, the semiconductor chips, and the solder mask patterns.