Insulated MOS Transistor Layout for Container Opening Detection
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Solution Overview
Problem
Existing technologies struggle to detect whether a closed container has been opened, especially when the cutting of an electrically conductive wire is followed by resolidification, which can falsely indicate the container remains sealed.
Innovation Solution
A system incorporating an integrated circuit with a MOS transistor having a double level of polysilicon, where the grid region is in the first level of polysilicon and the source, substrate, and drain regions are in the second level, allowing for detection of both present and past sectioning of a wire through voltage measurements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional MOS transistor structure is used with substrate-based source and drain regions, then the transistor can be easily manufactured using standard CMOS processes, but the transistor cannot be electrically isolated from the substrate which prevents accurate detection of wire sectioning
Solution Approach 1:
The transistor is segmented into two separate polysilicon levels: the first polysilicon level contains the gate region and is electrically isolated from the substrate, while the second polysilicon level contains the source and drain regions. This segmentation allows the transistor to be electrically isolated from the substrate while maintaining compatibility with standard CMOS manufacturing processes.
Solution Approach 2:
The invention moves the gate region to a different vertical dimension (first polysilicon level) separated from the substrate by an insulating trench, while keeping the source and drain regions in the second polysilicon level. This dimensional separation enables electrical isolation while preserving the transistor's functionality and compatibility with existing manufacturing processes.
2Ease of manufacture
If the first polysilicon region is heavily doped to ensure good electrical contact, then the manufacturing process is simplified, but leakage between source and drain regions increases
Solution Approach 1:
The transistor structure segments the gate region (first polysilicon level) from the source and drain regions (second polysilicon level), allowing independent doping optimization. The first polysilicon can be heavily doped for good gate electrical contact while the second polysilicon level maintains lower doping to minimize source-drain leakage.
Solution Approach 2:
Different doping concentrations are applied to different regions: the first polysilicon region is heavily doped to ensure good electrical contact for the gate, while the second polysilicon level with source and drain regions uses lower doping to reduce leakage current. This local quality differentiation resolves the contradiction between ease of manufacture and leakage reduction.
Data Source
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AI summary
The integrated circuit comprises -a first substrate (SB1) and -at least one first MOS transistor (TRP) having a first polysilicon region (P1) electrically isolated from the first substrate and including a gate region (RG), a second polysilicon region (P2) electrically isolated from the first polysilicon region (P1) and the first substrate (SB1) and including a source region (RS), a substrate region (RSB) and a drain region (RD) of said first transistor, the first polysilicon region (P1) being located between a zone (Z) of the first substrate (SB1) and the second polysilicon region (P2).