Heterogeneous Semiconductor Integration via Insulated Seed Layer
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Solution Overview
Problem
The integration of compound semiconductor (CS) devices on a non-semi-insulating silicon-based substrate poses challenges such as substrate conduction preventing complete transistor pinch-off, leading to lower AC gain, cutoff frequency, power density, and increased series resistance, which affects the performance of heterogeneously integrated CS and silicon CMOS FETs.
Innovation Solution
A semiconductor structure is designed with a substrate, a seed layer, an elemental semiconductor layer, and a compound semiconductor layer, where the seed layer is electrically insulated and contacted through vertical pillars to control local electrical potential, reducing the impact of interface charge layers and using low resistivity metal interconnects to minimize series resistance and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a CS epitaxial structure is grown on top of a seed layer with different crystal structure and electronic properties, then integration of CS devices on silicon substrate is achieved, but device performance deteriorates due to formation of unwanted interface layer between seed and CS layers
Solution Approach 1:
A buffer layer is introduced as an intermediary between the silicon seed layer and the compound semiconductor layer. This buffer layer acts as a mediator that gradually transitions the crystal structure and electronic properties from silicon to the compound semiconductor material, reducing the abrupt interface discontinuity and minimizing the formation of unwanted interface layers that would otherwise degrade device performance.
Solution Approach 2:
The composition and thickness of the buffer layer are optimized to gradually change the lattice constant and electronic properties from the silicon seed layer to the compound semiconductor layer. By controlling the buffer layer parameters (such as Ge content in SiGe buffer), the interface quality is improved while maintaining the ability to grow high-quality CS devices on silicon substrate.
2Adaptability or versatility
If CS devices are integrated onto non-semi-insulating silicon-based substrate, then heterogeneous integration is achieved, but substrate conduction prevents complete transistor pinch-off leading to lower AC gain, cutoff frequency, and power density
Solution Approach 1:
The substrate is functionally segmented into different regions: a non-semi-insulating silicon substrate for compatibility with CMOS processes, and a localized semi-insulating region created through the seed layer and buffer layer structure beneath the CS device. This segmentation allows the substrate to maintain overall non-semi-insulating properties for integration while providing local semi-insulating characteristics to enable complete transistor pinch-off and improve AC gain, cutoff frequency, and power density.
Solution Approach 2:
The seed layer and buffer layer structure provides local semi-insulating properties directly beneath the CS device active region, while the rest of the silicon substrate maintains its non-semi-insulating character. This local quality modification ensures that substrate conduction does not prevent complete transistor pinch-off in the CS device, thereby improving AC gain, cutoff frequency, and power density without compromising heterogeneous integration capability.
3Ease of manufacture
If conventional interconnect structures are used between CS and silicon CMOS FETs, then simple fabrication is maintained, but series resistance and shunt capacitance increase affecting device performance
Solution Approach 1:
The interconnect structure transitions from planar (2D) to vertical (3D) architecture. Vertical pillars extend downward from the CS device region to contact the seed layer, creating three-dimensional interconnect pathways. This dimensional change reduces the horizontal current path length and minimizes series resistance, while the vertical configuration reduces parasitic capacitance to surrounding structures, thereby improving interconnect performance without significantly complicating the fabrication process.
Solution Approach 2:
The seed layer serves as an intermediary conductive element between the CS device and the silicon substrate. By contacting the seed layer through vertical pillars, low-series-resistance interconnects are established. The seed layer acts as a mediator that provides a low-resistance pathway, reducing both series resistance and shunt capacitance in the interconnect between CS and silicon CMOS FETs.
Data Source
AI summary
A semiconductor structure comprising: a substrate; a seed layer supported by the substrate; an elemental semiconductor layer disposed over a first portion of the seed layer; and a compound semiconductor layer disposed on a second portion of the seed layer. The first portion of the seed layer is electrically insulated from the second portion of the seed layer. A first semiconductor device is formed in the elemental semiconductor layer. A second semiconductor device is formed in the compound semiconductor layer. The second semiconductor device includes: a first electrode in contact with a first region of the compound semiconductor layer; a second electrode in contact with a second region of the compound semiconductor layer; and a third electrode. The third electrode controls carriers passing in a third region of the compound semiconductor layer disposed between the first region and the second region. A fourth electrode is in electrical contact with the second portion of the seed layer.