Insulated Semiconductor Package Layout for High-Voltage Isolation
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Solution Overview
Problem
Conventional flat no-leads packages for high voltage semiconductor devices are large, costly, and have reduced reliability due to size constraints and increased parasitic inductance, necessitating improved packaging solutions that address clearance and creepage distance requirements.
Innovation Solution
A semiconductor device with a substrate having an electrically-insulating material and patterned conductive formations, allowing for electrical insulation between die pads and leads, reducing the need for large package sizes and enabling closer die placement, thus minimizing parasitic inductance and thermal resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flat no-leads packages are used for high voltage semiconductor devices, then electrical insulation between die pads and leads is achieved, but package size becomes large due to clearance and creepage distance requirements
Solution Approach 1:
The patent transitions from a conventional planar leadframe structure to a three-dimensional stacked package architecture. Multiple semiconductor dies are vertically stacked and interconnected through through-silicon vias (TSVs), allowing electrical connections to pass through the substrate thickness rather than traveling laterally across the package surface. This dimensional change enables high voltage isolation within the vertical axis while maintaining a compact footprint on the PCB.
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor dies are stacked one on top of another, with each die containing functional elements embedded within its structure. The through-silicon vias nest through the substrate thickness, and the overall package nests multiple functional layers in a compact vertical arrangement, significantly reducing the horizontal package area while maintaining all necessary electrical isolation distances.
2Reliability
If die pads are positioned at safe distances to meet insulation requirements, then electrical insulation is maintained, but parasitic inductance increases
Solution Approach 1:
The patent resolves the inductance issue by moving electrical connections from the horizontal plane to the vertical dimension. Through-silicon vias provide direct vertical pathways for current flow between stacked dies, dramatically shortening the current loop areas and reducing parasitic inductance. This vertical interconnection approach maintains electrical isolation between high voltage and low voltage circuits while minimizing the harmful inductive effects that would otherwise require large separation distances.
3Reliability
If clearance and creepage distances are increased for high voltage applications, then insulation compliance is achieved, but manufacturing cost increases
Solution Approach 1:
The patent achieves insulation compliance in the horizontal plane by utilizing vertical separation through the substrate thickness. The through-silicon vias and stacked die architecture provide inherent high voltage isolation within the Z-dimension, allowing the package footprint to be minimized. This approach eliminates the need for expensive large-format substrates or additional insulation layers, reducing manufacturing costs while maintaining full compliance with high voltage clearance and creepage requirements.
Data Source
AI summary
A packaged semiconductor device includes a substrate having a first surface and a second surface opposite the first surface. At least one semiconductor die is mounted at the first surface of the substrate. Electrically-conductive leads are arranged around the substrate, and electrically-conductive formations couple the at least one semiconductor die to selected leads of the electrically-conductive leads. A package molding material is molded onto the at least one semiconductor die, onto the electrically-conductive leads and onto the electrically-conductive formations. The package molding material leaves the second surface of the substrate uncovered by the package molding material. The substrate is formed by a layer of electrically-insulating material.